External Memory Interfaces Agilex™ 7 M-Series FPGA IP Core Release Notes

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Date 7/15/2024
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1. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Release Notes
1. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Release Notes x
1.1. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v6.2.0 1.2. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v6.1.0 1.3. External Memory Interfaces Agilex™ 7 M-Series FPGA IP v6.0.0 1.4. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP v5.0.0 1.5. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP v4.0.0 1.6. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP v3.0.0
1. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Release Notes

1.6. External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP v3.0.0

Table 26.  v3.0.0 2023.04.03
Description Impact
Verified in the Quartus® Prime software v23.1. Provides external memory interface IP for DDR4, DDR5, and LPDDR5 external memory for Intel Agilex® 7 M-Series devices. The tables that follow summarize speed and feature support.
Note: This documentation is preliminary and subject to change.
Note: Device support for Intel Agilex® 7 M-series FPGAs and SoCs in the Quartus® Prime Pro Edition software version 23.1 is restricted. To enable M-series device support in your instance of the Quartus® Prime Pro Edition software, contact your regional Intel FPGA sales representative.
Table 27.   Intel Agilex® 7 M-Series Fabric EMIF IP Speed Support Summary
      Max Rate (Mbps/MHz)   -1 -2 -3
Protocol Category Subcategory -1 -2 -3 Support Detail S C T H S C T H S C T H
DDR4 Memory Format Component 3200/1600 (1R) 3200/1600 (1R) 2666/1333 (1R)           X 1 X X 3   X 1 X X 3  
2666/1333 (2R) 2666/1333 (2R) 2400/1200 (2R)           X 1 X X 3   X 1 X X 3  
DDR5 Memory Format Component 3200/1600 (1R) 2 3200/1600 (1R) 2 3200/1600 (1R) 2           X 1 X X 3   X 1 X X 3  
3200/1600 (2R) 2 3200/1600 (2R) 2 3200/1600 (2R) 2           X 1 X X 3   X 1 X X 3  
UDIMM 3200/1600 (1DPC 1R) 2 3200/1600 (1DPC 1R) 2 3200/1600 (1DPC 1R) 2           X 1 X X 3   X 1 X X 3  
3200/1600 (1DPC 2R) 2 3200/1600 (1DPC 2R) 2 3200/1600 (1DPC 2R) 2           X 1 X X 3   X 1 X X 3  
SODIMM 3200/1600 (1DPC 1R) 2 3200/1600 (1DPC 1R) 2 3200/1600 (1DPC 1R) 2           X 1 X X 3   X 1 X X 3  
3200/1600 (1DPC 2R) 2 3200/1600 (1DPC 2R) 2 3200/1600 (1DPC 2R) 2           X 1 X X 3   X 1 X X 3  
LPDDR5 Memory Format Component 3200/1600 (1R) 2 3200/1600 (1R) 2 3200/1600 (1R) 2           X 1 X X 3   X 1 X X 3  
3200/1600 (2R) 2 3200/1600 (2R) 2 3200/1600 (2R) 2           X 1 X X 3   X 1 X X 3  
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
  • 1 = Supports VCS and QuestaSim.
  • 2 = Current performance in the Quartus® Prime software. Check the External Memory Interface Spec Estimator for production performance.
  • 3 = Timing is currently preliminary. It will be necessary to recompile designs in future releases.

Note: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.
Table 28.   Intel Agilex® 7 M-Series Fabric EMIF IP Feature Support Summary
Protocol Category Sub-Category Supported? S C T H
DDR4 Interface Width 16, 16+ECC, 32, 32+ECC X X X X  
SODIMM, UDIMM          
RDIMM          
Controller Hard controller X X X X  
3DS 3DS          
Design Example   X X X X  
DBI Read DBI          
Write DBI X X X X  
Mirroring Address mirroring for odd ranks for multi-rank DIMMs          
DM DM pins X X X X  
Preamble Read preamble settings          
Write preamble settings          
AXI access mode Fabric sync mode X X X X  
Fabric async mode X X X X  
NoC X X X X  
Debug EMIF Toolkit          
Simulation Abstract PHY          
Simulators 1 VCS X X      
VCS-MX X X      
ModelSim SE X X      
Xcelium          
Aldec          
DDR5 Interface Width 16, 16+ECC, 32, 32+ECC X X X X  
SODIMM, UDIMM X X X X  
RDIMM          
Controller Hard controller X X X X  
3DS 3DS          
Design Example   X X X X  
DM DM pins X X X X  
Preamble Read preamble settings          
Write preamble settings          
AXI access mode Fabric sync mode X X X X  
Fabric async mode X X X X  
NoC X X X X  
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS X X      
VCS-MX X X      
ModelSim SE X X      
Xcelium          
Aldec          
LPDDR5 Interface Width 32 X X X X  
16 X X X X  
Controller Hard controller X X X X  
Design Example   X X X X  
DBI Read DBI          
Write DBI X X X X  
Mirroring Address mirroring for odd ranks for multi rank DIMMs          
DM DM pins X X X X  
Preamble Read preamble settings          
Write preamble settings          
AXI access mode Fabric sync mode X X X X  
Fabric async mode X X X X  
NoC X X X X  
Debug EMIF toolkit          
Simulation Abstract PHY          
Simulators 1 VCS X X      
VCS-MX X X      
ModelSim SE X X      
Xcelium          
Aldec          
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = VHDL is not supported.
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