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Answers to Top FAQs
1. Parameterizable Macros for Intel FPGAs Overview
2. Dual-Port Random Access Memory (RAM) Parameterizable Macros
3. FIFO Parameterizable Macros
4. I/O PLL Parameterizable Macro (ipm_iopll)
5. CDC Parameterizable Macros
6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
7. Parameterizable Macros for Intel FPGAs User Guide Archives
2.1.1. Simple Dual-Port RAM Parameterizable Macro Port Descriptions
2.1.2. Simple Dual-Port RAM Parameterizable Macro Parameters
2.1.3. Simple Dual-Port RAM VHDL Instantiation Template
2.1.4. Simple Dual-Port RAM Verilog Instantiation Template
2.1.5. Simple Dual-Port RAM SystemVerilog Instantiation Template
5.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst)
5.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst)
5.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync)
5.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync)
5.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux)
5.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync)
5.7. Pulse Synchronizer Parameterizable Macro (ipm_cdc_pulse_sync)
5.1.1. Synchronous Reset Synchronizer Parameterizable Macro Port Descriptions
5.1.2. Synchronous Reset Synchronizer Parameterizable Macro Parameters
5.1.3. Synchronous Reset Synchronizer VHDL Instantiation Template
5.1.4. Synchronous Reset Synchronizer Verilog Instantiation Template
5.1.5. Synchronous Reset Synchronizer SystemVerilog Instantiation Template
5.2.1. Asynchronous Reset Synchronizer Parameterizable Macro Port Descriptions
5.2.2. Asynchronous Reset Synchronizer Parameterizable Macro Parameters
5.2.3. Asynchronous Reset Synchronizer VHDL Instantiation Template
5.2.4. Asynchronous Reset Synchronizer Verilog Instantiation Template
5.2.5. Asynchronous Reset Synchronizer SystemVerilog Instantiation Template
5.3.1. Synchronizer Using Single Clock Parameterizable Macro Port Descriptions
5.3.2. Synchronizer Using Single Clock Parameterizable Macro Parameters
5.3.3. Synchronizer Using Single Clock VHDL Instantiation Template
5.3.4. Synchronizer Using Single Clock Verilog Instantiation Template
5.3.5. Synchronizer Using Single Clock SystemVerilog Instantiation Template
5.4.1. Synchronizer Using Two Clocks Parameterizable Macro Port Descriptions
5.4.2. Synchronizer Using Two Clocks Parameterizable Macro Parameters
5.4.3. Synchronizer Using Two Clocks VHDL Instantiation Template
5.4.4. Synchronizer Using Two Clocks Verilog Instantiation Template
5.4.5. Synchronizer Using Two Clocks SystemVerilog Instantiation Template
5.5.1. Glitchless Clock MUX Parameterizable Macro Port Descriptions
5.5.2. Glitchless Clock MUX Parameterizable Macro Parameters
5.5.3. Glitchless Clock MUX VHDL Instantiation Template
5.5.4. Glitchless Clock MUX Verilog Instantiation Template
5.5.5. Glitchless Clock MUX SystemVerilog Instantiation Template
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2.2.2. True Dual-Port RAM Parameterizable Macro Parameters
Name | Allowed Values | Description |
---|---|---|
ADDR_WIDTH_A | Device and DATA_WIDTH_A dependent | Specifies the width of the usedw port. The default value is 11. |
ADDR_WIDTH_B | Device and DATA_WIDTH_B dependent | Specifies the width of the usedw port. The default value is 11. |
BYTE_EN_WIDTH_A | 1 | Width of the byte enable bus at Port A. The width for BYTE_EN_WIDTH_A should be equal to DATA_WIDTH_A divided by BYTE_SIZE. |
BYTE_EN_WIDTH_B | 1 | Width of the byte-enable bus at Port B. This width should be equal to DATA_WIDTH_B divided by BYTE_SIZE. |
BYTE_SIZE | 5 8 9 10 |
Specifies the size of the byte for byte-enable mode. |
IN_CLK_EN_A | NORMAL BYPASS |
Specifies the clock enable for the input registers of Port A. |
IN_CLK_EN_B | NORMAL BYPASS |
Specifies the clock enable for the input registers of Port B. |
OUT_CLK_EN_A | NORMAL BYPASS |
Specifies the clock enable for the output registers of Port A. |
OUT_CLK_EN_B | NORMAL BYPASS |
Specifies the clock enable for the output registers of Port B. |
DATA_WIDTH_A | Device and ADDR_WIDTH_A dependent | Specifies the width of the data and q ports. The default value is 8. |
DATA_WIDTH_B | Device and ADDR_WIDTH_B dependent | Specifies the width of the data and q ports. The default value is 8. |
INIT_FILE_LAYOUT | PORT_A PORT_B |
Specifies the layout of the initialization file. |
MAX_DEPTH | 2048 | Specifies the depth of the RAM slices. |
INIT_FILE | *.mif *.hex |
Specifies the initialization file. |
OUT_DATA_ACLR_A | NONE CLEAR0 |
Asynchronous clear choice for data output registers at Port A. When OUT_DATA_REG_CLK_A is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch. |
OUT_DATA_SCLR_A | NONE SCLEAR |
Synchronous clear choice for data output registers at Port A. When OUT_DATA_REG_CLK_A is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch. |
OUT_DATA_ACLR_B | NONE CLEAR0 |
Asynchronous clear choice for data output registers at Port B. When OUT_DATA_REG_CLK_B is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch. |
OUT_DATA_SCLR_B | NONE SCLEAR |
Synchronous clear choice for data output registers at Port B. When OUT_DATA_REG_CLK_B is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch. |
OUT_DATA_REG_CLK_A | UNREGISTERED CLOCK1 CLOCK0 |
Clock choice for data output registers at Port A. |
OUT_DATA_REG_CLK_B | UNREGISTERED CLOCK1 CLOCK0 |
Clock choice for data output registers at Port B. |
READ_DURING_WRITE_MODE_A | NEW_DATA_NO_NBE_READ |
The behavior of read-during-write mode in Port A. |
READ_DURING_WRITE_MODE_B | NEW_DATA_NO_NBE_READ |
The behavior of read-during-write mode in Port B. |