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Answers to Top FAQs
1. Parameterizable Macros for Intel FPGAs Overview
2. Dual-Port Random Access Memory (RAM) Parameterizable Macros
3. FIFO Parameterizable Macros
4. I/O PLL Parameterizable Macro (ipm_iopll)
5. CDC Parameterizable Macros
6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
7. Parameterizable Macros for Intel FPGAs User Guide Archives
2.1.1. Simple Dual-Port RAM Parameterizable Macro Port Descriptions
2.1.2. Simple Dual-Port RAM Parameterizable Macro Parameters
2.1.3. Simple Dual-Port RAM VHDL Instantiation Template
2.1.4. Simple Dual-Port RAM Verilog Instantiation Template
2.1.5. Simple Dual-Port RAM SystemVerilog Instantiation Template
5.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst)
5.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst)
5.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync)
5.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync)
5.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux)
5.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync)
5.7. Pulse Synchronizer Parameterizable Macro (ipm_cdc_pulse_sync)
5.1.1. Synchronous Reset Synchronizer Parameterizable Macro Port Descriptions
5.1.2. Synchronous Reset Synchronizer Parameterizable Macro Parameters
5.1.3. Synchronous Reset Synchronizer VHDL Instantiation Template
5.1.4. Synchronous Reset Synchronizer Verilog Instantiation Template
5.1.5. Synchronous Reset Synchronizer SystemVerilog Instantiation Template
5.2.1. Asynchronous Reset Synchronizer Parameterizable Macro Port Descriptions
5.2.2. Asynchronous Reset Synchronizer Parameterizable Macro Parameters
5.2.3. Asynchronous Reset Synchronizer VHDL Instantiation Template
5.2.4. Asynchronous Reset Synchronizer Verilog Instantiation Template
5.2.5. Asynchronous Reset Synchronizer SystemVerilog Instantiation Template
5.3.1. Synchronizer Using Single Clock Parameterizable Macro Port Descriptions
5.3.2. Synchronizer Using Single Clock Parameterizable Macro Parameters
5.3.3. Synchronizer Using Single Clock VHDL Instantiation Template
5.3.4. Synchronizer Using Single Clock Verilog Instantiation Template
5.3.5. Synchronizer Using Single Clock SystemVerilog Instantiation Template
5.4.1. Synchronizer Using Two Clocks Parameterizable Macro Port Descriptions
5.4.2. Synchronizer Using Two Clocks Parameterizable Macro Parameters
5.4.3. Synchronizer Using Two Clocks VHDL Instantiation Template
5.4.4. Synchronizer Using Two Clocks Verilog Instantiation Template
5.4.5. Synchronizer Using Two Clocks SystemVerilog Instantiation Template
5.5.1. Glitchless Clock MUX Parameterizable Macro Port Descriptions
5.5.2. Glitchless Clock MUX Parameterizable Macro Parameters
5.5.3. Glitchless Clock MUX VHDL Instantiation Template
5.5.4. Glitchless Clock MUX Verilog Instantiation Template
5.5.5. Glitchless Clock MUX SystemVerilog Instantiation Template
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5.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux)
The glitchless clock MUX parameterizable macro (ipm_cdc_glitchless_clk_mux) supports designs with multi-frequency clocks. Such design commonly require switching the clock source while the design is running. You can implement this clock switching by multiplexing two different frequency clock sources in hardware and controlling the multiplexer select line with internal logic. The two clock frequencies that you switch can be totally unrelated to each other, or they may be multiples of each other.
The glitchless clock mux macro allows you to avoid a glitch at the output of the clock line of a switch by specifying the relation of the input clocks with the CLK_TYPE parameter. Use the CLK_TYPE parameter to specify whether clocks are related (RELATED_CLKS) or unrelated (UNRELATED_CLKS).
If you parameterize the clock mux for related clocks, and feed it with clocks that are actually unrelated—the output may glitch.
Figure 11. Glitchless Clock Mux Parameterizable Macro Block Diagram
To ensure that the switchover occurs properly, the two clocks that feed the glitchless clock mux must be toggling before and after the select input changes. If the clocks stop toggling too soon, the switchover does not occur.
The switchover circuitry differs, depending on whether you parameterize the mux for related or unrelated clocks. Related clocks are multiples of one another. Based on the period of the clocks, there is a delay from the time the select input changes, until the changed clock is reflected at the output.
- When you parameterize the clock mux for related clocks, and the select input changes—the delay is equal to the time to the next falling edge of the active clock, then the time to the next falling edge of the newly selected clock.
- When you parameterize the clock mux for unrelated clocks, and the select input changes— the delay is equal to the time to the second falling edge of the active clock, then the time to the second falling edge of the newly selected clock.