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1. Agilex™ 7 M-Series General-Purpose I/O Overview
2. Agilex™ 7 M-Series GPIO-B Banks
3. Agilex™ 7 M-Series HPS I/O Banks
4. Agilex™ 7 M-Series SDM I/O Banks
5. Agilex™ 7 M-Series I/O Troubleshooting Guidelines
6. GPIO Intel® FPGA IP
7. Programmable I/O Features Description
8. Documentation Related to the Agilex™ 7 General-Purpose I/O User Guide: M-Series
9. Agilex™ 7 General-Purpose I/O User Guide: M-Series Archives
10. Document Revision History for the Agilex™ 7 General-Purpose I/O User Guide: M-Series
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os
2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank
2.5.3. VREF Sources and Input Standards Grouping
2.5.4. GPIO-B Pin Restrictions for External Memory Interfaces
2.5.5. RZQ Pin Requirement
2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.8. Simultaneous Switching Noise
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. SDM Shared I/O Requirements
2.5.12. Unused Pins
2.5.13. VCCIO_PIO Supply for Unused GPIO-B Banks
2.5.14. GPIO-B Pins During Power Sequencing
2.5.15. Drive Strength Requirement for GPIO-B Input Pins
2.5.16. Maximum DC Current Restrictions
2.5.17. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
2.5.18. Connection to True Differential Signaling Input Buffers During Device Reconfiguration
2.5.19. LVSTL700 I/O Standards Differential Pin Pair Requirements
2.5.20. Implementing a Pseudo Open Drain
2.5.21. Allowed Duration for Using RT OCT
2.5.22. Single-Ended Strobe Signal Differential Pin Pair Restriction
2.5.23. Implementing SLVS-400 Standard at 1.1 V VCCIO_PIO Sub-bank
6.1. Release Information for GPIO Intel® FPGA IP
6.2. Generating the GPIO Intel® FPGA IP
6.3. GPIO Intel® FPGA IP Parameter Settings
6.4. GPIO Intel® FPGA IP Interface Signals
6.5. GPIO Intel® FPGA IP Architecture
6.6. Verifying Resource Utilization and Design Performance
6.7. GPIO Intel® FPGA IP Timing
6.8. GPIO Intel® FPGA IP Design Examples
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2.4.1.3. Single-Ended I/O Standards External Termination
The SSTL, HSTL, POD, and LVSTL I/O standards require a termination voltage. The internally-generated reference voltage of the receiving device tracks the termination voltage of the transmitting device.
Altera recommends that you use OCT with these I/O standards to save board space and cost. OCT reduces the number of external termination resistors required.
Note: You cannot use RS and RT OCT simultaneously. For more information, refer to the related information.
I/O Standard | External Termination Scheme |
---|---|
1.3 V LVCMOS | No on-board termination required |
1.2 V LVCMOS | No on-board termination required |
1.1 V LVCMOS | No on-board termination required |
1.05 V LVCMOS | No on-board termination required |
SSTL-12 | Single-ended SSTL I/O standard termination |
HSTL-12 | Single-ended HSTL I/O standard termination |
HSUL-12 | No on-board termination required |
POD12 | Single-ended POD I/O standard termination |
POD11 | Single-ended POD I/O standard termination |
LVSTL11 | Single-ended LVSTL I/O standard termination |
LVSTL105 | Single-ended LVSTL I/O standard termination |
LVSTL700 | Single-ended LVSTL I/O standard termination |
Differential SSTL-12 | Differential SSTL I/O standard termination |
Differential HSTL-12 | Differential HSTL I/O standard termination |
Differential HSUL-12 | No on-board termination required |
Differential POD12 | Differential POD I/O standard termination |
Differential POD11 | Differential POD I/O standard termination |
Differential LVSTL11 | Differential LVSTL I/O standard termination |
Differential LVSTL105 | Differential LVSTL I/O standard termination |
Differential LVSTL700 | Differential LVSTL I/O standard termination |
Figure 11. SSTL and HSTL I/O Standards External Termination
Figure 12. POD I/O Standards External Termination
Figure 13. LVSTL I/O Standards External Termination
Related Information