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1. Agilex™ 7 M-Series General-Purpose I/O Overview
2. Agilex™ 7 M-Series GPIO-B Banks
3. Agilex™ 7 M-Series HPS I/O Banks
4. Agilex™ 7 M-Series SDM I/O Banks
5. Agilex™ 7 M-Series I/O Troubleshooting Guidelines
6. GPIO Intel® FPGA IP
7. Programmable I/O Features Description
8. Documentation Related to the Agilex™ 7 General-Purpose I/O User Guide: M-Series
9. Agilex™ 7 General-Purpose I/O User Guide: M-Series Archives
10. Document Revision History for the Agilex™ 7 General-Purpose I/O User Guide: M-Series
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os
2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank
2.5.3. VREF Sources and Input Standards Grouping
2.5.4. GPIO-B Pin Restrictions for External Memory Interfaces
2.5.5. RZQ Pin Requirement
2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.8. Simultaneous Switching Noise
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. SDM Shared I/O Requirements
2.5.12. Unused Pins
2.5.13. VCCIO_PIO Supply for Unused GPIO-B Banks
2.5.14. GPIO-B Pins During Power Sequencing
2.5.15. Drive Strength Requirement for GPIO-B Input Pins
2.5.16. Maximum DC Current Restrictions
2.5.17. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
2.5.18. Connection to True Differential Signaling Input Buffers During Device Reconfiguration
2.5.19. LVSTL700 I/O Standards Differential Pin Pair Requirements
2.5.20. Implementing a Pseudo Open Drain
2.5.21. Allowed Duration for Using RT OCT
2.5.22. Single-Ended Strobe Signal Differential Pin Pair Restriction
2.5.23. Implementing SLVS-400 Standard at 1.1 V VCCIO_PIO Sub-bank
6.1. Release Information for GPIO Intel® FPGA IP
6.2. Generating the GPIO Intel® FPGA IP
6.3. GPIO Intel® FPGA IP Parameter Settings
6.4. GPIO Intel® FPGA IP Interface Signals
6.5. GPIO Intel® FPGA IP Architecture
6.6. Verifying Resource Utilization and Design Performance
6.7. GPIO Intel® FPGA IP Timing
6.8. GPIO Intel® FPGA IP Design Examples
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2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank
If you use true differential I/O standards and single-ended I/O standards in the same or adjacent GPIO-B banks, adhere to the following placement guidelines. These restrictions do not apply to differential reference clock that feeds directly into the PLL reference clock ports.
- Do not place true differential and toggling single-ended I/O standards in the combinations of locations listed in the following tables.
- From version 24.1, the Quartus® Prime software issues the following errors:
- Compilation error—violation of the same bank placement restriction.
- Critical warning—assignment of true differential I/O standards to pin pairs with the following pin index numbers: 0 and 1, 6 and 7, 88 and 89, and 94 and 95.
Combinations Not Allowed (Pin Index Number) | Combinations Not Allowed (Pin Index Number) | Combinations Not Allowed (Pin Index Number) | Combinations Not Allowed (Pin Index Number) | ||||
---|---|---|---|---|---|---|---|
True Differential Pin Pair | Single-Ended Pin | True Differential Pin Pair | Single-Ended Pin | True Differential Pin Pair | Single-Ended Pin | True Differential Pin Pair | Single-Ended Pin |
0 and 1 | 2 | 24 and 25 | 17, 26 | 48 and 49 | 41, 50 | 72 and 73 | 65, 74 |
2 and 3 | 1, 4 | 26 and 27 | 25, 28 | 50 and 51 | 49, 52 | 74 and 75 | 73, 76 |
4 and 5 | 3, 12 | 28 and 29 | 27, 36 | 52 and 53 | 51, 60 | 76 and 77 | 75, 84 |
6 and 7 | 8 | 30 and 31 | 23, 32 | 54 and 55 | 47, 56 | 78 and 79 | 71, 80 |
8 and 9 | 7, 10 | 32 and 33 | 31, 34 | 56 and 57 | 55, 58 | 80 and 81 | 79. 82 |
10 and 11 | 9, 18 | 34 and 35 | 33, 42 | 58 and 59 | 57, 66 | 82 and 83 | 81, 90 |
12 and 13 | 5, 14 | 36 and 37 | 29, 38 | 60 and 61 | 53, 62 | 84 and 85 | 77, 86 |
14 and 15 | 13, 16 | 38 and 39 | 37, 40 | 62 and 63 | 61, 64 | 86 and 87 | 85, 88 |
16 and 17 | 15, 24 | 40 and 41 | 39, 48 | 64 and 65 | 63, 72 | 88 and 89 | 87 |
18 and 19 | 11, 20 | 42 and 43 | 35, 44 | 66 and 67 | 59, 68 | 90 and 91 | 83, 92 |
20 and 21 | 19, 22 | 44 and 45 | 43, 46 | 68 and 69 | 67, 70 | 92 and 93 | 91, 94 |
22 and 23 | 21, 30 | 46 and 47 | 45, 54 | 70 and 71 | 69, 78 | 94 and 95 | 93 |
Combinations Not Allowed (Pin Index Number) | Combinations Not Allowed (Pin Index Number) | ||||||
---|---|---|---|---|---|---|---|
True Differential | Single-Ended | True Differential | Single-Ended | ||||
Bank | Pin Pair | Bank | Pin | Bank | Pin Pair | Bank | Pin |
3A | 88 and 89 | 3B | 0 | 2A | 88 and 89 | 2B | 89 |
94 and 95 | 6 | 94 and 95 | 95 | ||||
3B | 0 and 1 | 3A | 89 | 2B | 0 and 1 | 2C | 89 |
6 and 7 | 95 | 6 and 7 | 95 | ||||
88 and 89 | 3C | 89 | 88 and 89 | 2A | 89 | ||
94 and 95 | 95 | 94 and 95 | 95 | ||||
3C | 0 and 1 | 3D | 89 | 2C | 0 and 1 | 2D | 89 |
6 and 7 | 95 | 6 and 7 | 95 | ||||
88 and 89 | 3B | 89 | 88 and 89 | 2B | 0 | ||
94 and 95 | 95 | 94 and 95 | 6 | ||||
3D | 88 and 89 | 3C | 0 | 2D | 88 and 89 | 2C | 0 |
94 and 95 | 6 | 94 and 95 | 6 |
Refer to the related information for the figure showing the locations of the GPIO-B banks.
Related Information