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1. Agilex™ 7 M-Series General-Purpose I/O Overview
2. Agilex™ 7 M-Series GPIO-B Banks
3. Agilex™ 7 M-Series HPS I/O Banks
4. Agilex™ 7 M-Series SDM I/O Banks
5. Agilex™ 7 M-Series I/O Troubleshooting Guidelines
6. GPIO Intel® FPGA IP
7. Programmable I/O Features Description
8. Documentation Related to the Agilex™ 7 General-Purpose I/O User Guide: M-Series
9. Agilex™ 7 General-Purpose I/O User Guide: M-Series Archives
10. Document Revision History for the Agilex™ 7 General-Purpose I/O User Guide: M-Series
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os
2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank
2.5.3. VREF Sources and Input Standards Grouping
2.5.4. GPIO-B Pin Restrictions for External Memory Interfaces
2.5.5. RZQ Pin Requirement
2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.8. Simultaneous Switching Noise
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. SDM Shared I/O Requirements
2.5.12. Unused Pins
2.5.13. VCCIO_PIO Supply for Unused GPIO-B Banks
2.5.14. GPIO-B Pins During Power Sequencing
2.5.15. Drive Strength Requirement for GPIO-B Input Pins
2.5.16. Maximum DC Current Restrictions
2.5.17. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
2.5.18. Connection to True Differential Signaling Input Buffers During Device Reconfiguration
2.5.19. LVSTL700 I/O Standards Differential Pin Pair Requirements
2.5.20. Implementing a Pseudo Open Drain
2.5.21. Allowed Duration for Using RT OCT
2.5.22. Single-Ended Strobe Signal Differential Pin Pair Restriction
2.5.23. Implementing SLVS-400 Standard at 1.1 V VCCIO_PIO Sub-bank
6.1. Release Information for GPIO Intel® FPGA IP
6.2. Generating the GPIO Intel® FPGA IP
6.3. GPIO Intel® FPGA IP Parameter Settings
6.4. GPIO Intel® FPGA IP Interface Signals
6.5. GPIO Intel® FPGA IP Architecture
6.6. Verifying Resource Utilization and Design Performance
6.7. GPIO Intel® FPGA IP Timing
6.8. GPIO Intel® FPGA IP Design Examples
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6.2. Generating the GPIO Intel® FPGA IP
Using the GPIO Intel® FPGA IP parameter editor, you can customize the IP settings and generate the IP variant files, simulation testbench, and HDL instantiation template.
Before you begin, create or open a Quartus® Prime project.
Figure 28. GPIO Intel® FPGA IP Parameter Editor
- In the IP Catalog window, double-click GPIO Intel® FPGA IP .
The Parameter Editor window appears.
- Specify a top-level name for your new IP variant and click Create.
Do not include space and special characters in the name and file path.
- Set the values in the Parameters tab.
The System Messages tab displays errors and warning for the parameters settings.
- From the Parameter Editor menu, select File > Save.
The parameter editor saves the IP variant settings in the <your_ip> .ip file.
- To generate the IP variant HDL files:
- Click Generate HDL.
The Generation window appears.
- Specify the output file generation options and click Generate.
The parameter editor generates the synthesis and simulation files as you specified, and automatically adds the .ip file of the variant to your project.
- Click Close.
- Click Generate HDL.
- To generate a simulation testbench:
- From the Parameter Editor menu, select Generate > Generate Testbench System.
- Specify the testbench generation options and click Generate.
- Click Close.
- To generate an HDL instantiation template that you can copy and paste into your text editor:
- From the Parameter Editor menu, select Generate > Show Instantiation Template.
- Select the HDL Language.
The code template appears in the Example HDL box.
- Click Copy and then click Close.
After generating and instantiating your IP variant, assign appropriate pins to connect the ports.