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1. FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the FPGA AI Suite PCIe* -based Design Example
4. Building the FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Agilex™ 7 FPGA
A. FPGA AI Suite PCIe-based Design Example User Guide Archives
B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
5.1. Exporting Trained Graphs from Source Frameworks
5.2. Compiling Exported Graphs Through the FPGA AI Suite
5.3. Compiling the PCIe* -based Example Design
5.4. Programming the FPGA Device ( Agilex™ 7)
5.5. Performing Accelerated Inference with the dla_benchmark Application
5.6. Running the Ported OpenVINO™ Demonstration Applications
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4.1. CMake Targets
The top level CMake build target is the FPGA AI Suite runtime plugin shared library, libcoreDLARuntimePlugin.so. It will not be built if the target is the software reference. Details on how to target one of the example design boards or the software reference are specified in Build Options. The source files used to build the libcoreDLARuntimePlugin.so target are located under the following directories:
- runtime/plugin/src/
- runtime/coredla_device/src/
The flow also builds additional targets as dependencies for the top-level target. The most significant additional targets are as follows:
- The Input and Output Layout Transform library, libdliaPluginIOTransformations.a. The sources for this target are under runtime/plugin/io_transformations/.