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1. FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the FPGA AI Suite PCIe* -based Design Example
4. Building the FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Agilex™ 7 FPGA
A. FPGA AI Suite PCIe-based Design Example User Guide Archives
B. FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
5.1. Exporting Trained Graphs from Source Frameworks
5.2. Compiling Exported Graphs Through the FPGA AI Suite
5.3. Compiling the PCIe* -based Example Design
5.4. Programming the FPGA Device ( Agilex™ 7)
5.5. Performing Accelerated Inference with the dla_benchmark Application
5.6. Running the Ported OpenVINO™ Demonstration Applications
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6.3.3. BSP Driver
The FPGA AI Suite runtime MMD software uses a driver supplied as part of the BSP to access and interact with the FPGA device.
The source files for the driver are in runtime/coredla_device/mmd. The source files contain classes for managing and accessing the FPGA device by using BSP functions for reading/writing to CSR, reading/writing to DDR, and handling kernel interrupts.
BSP Driver for the Agilex™ 7 Design Example
Contact your Intel representative for information on the driver for the Terasic DE10-Agilex board support package.
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