FPGA AI Suite: IP Reference Manual

Download PDF
ID 768974
Date 4/21/2025
Public

Visible to Intel only — GUID: bub1719420965518

Ixiasoft

View Details

Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite IP Reference Manual 2. About the FPGA AI Suite IP 3. FPGA AI Suite IP Generation Utility 4. FPGA AI Suite Ahead-of-Time Splitter Utility 5. CSR Map and Descriptor Queue A. FPGA AI Suite IP Reference Manual Archives B. FPGA AI Suite IP Reference Manual Document Revision History
2. About the FPGA AI Suite IP x
2.1. Supported Models 2.2. Model Performance 2.3. Software Emulation of the FPGA AI Suite IP 2.4. FPGA AI Suite Layer / Primitive Ranges 2.5. FPGA AI Suite IP Block Configuration 2.6. IP Block Interfaces 2.7. Feature Input and Output Streaming 2.8. DDR-Free Operation
2.1. Supported Models x
2.1.1. MobileNet V2 differences between Caffe and TensorFlow models
2.2. Model Performance x
2.2.1. Throughput on the MobileNetV1 model (and other very fast models) 2.2.2. DDR-Free Streaming Performance
2.5. FPGA AI Suite IP Block Configuration x
2.5.1. Architecture Description File Format for Instance Parameterization 2.5.2. Architecture Description File Parameters
2.5.2. Architecture Description File Parameters x
2.5.2.1. Parameter Group: Global Parameters 2.5.2.2. Parameter Group: activation 2.5.2.3. Parameter Group: pe_array 2.5.2.4. Parameter Group: pool 2.5.2.5. Parameter Group: depthwise 2.5.2.6. Module: softmax 2.5.2.7. Parameter Group: dma 2.5.2.8. Parameter Group: xbar 2.5.2.9. Parameter Group: filter_scratchpad 2.5.2.10. Parameter Group: input_stream_interface 2.5.2.11. Parameter Group: output_stream_interface 2.5.2.12. Parameter Group: config_network 2.5.2.13. Parameter Group: layout_transform_params
2.6. IP Block Interfaces x
2.6.1. Clock and Reset 2.6.2. AXI Interfaces 2.6.3. AXI Interface Clock and Reset 2.6.4. Input Feature Tensor In-Memory Format 2.6.5. Output Tensor In-Memory Format
2.6.4. Input Feature Tensor In-Memory Format x
2.6.4.1. Multiple Input Graphs 2.6.4.2. Input Folding 2.6.4.3. Input Scale and Shift 2.6.4.4. Input Transform Mapping 2.6.4.5. Input Layout Transform Hardware
2.7. Feature Input and Output Streaming x
2.7.1. Input Streaming 2.7.2. Output Streaming
3. FPGA AI Suite IP Generation Utility x
3.1. IP Generation Utility Execution Flows 3.2. IP Generation Utility Inputs 3.3. IP Generation Utility Outputs 3.4. IP Generation Utility Command Line Options
3.4. IP Generation Utility Command Line Options x
3.4.1. The --flow create_ip Flow 3.4.2. The --flow add_arch Flow 3.4.3. The --flow list Flow 3.4.4. The --flow remove_arch Flow
4. FPGA AI Suite Ahead-of-Time Splitter Utility x
4.1. Files Generated by the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.2. Building the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.3. Running the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.4. FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility Example Application
5. CSR Map and Descriptor Queue x
5.1. Discovery ROM 5.2. Interrupt Control 5.3. DMA Descriptor Queue 5.4. DMA Control Registers 5.5. Performance Registers 5.6. Debug Network Registers 5.7. DMA License Register 5.8. DMA Transaction Counters
1. FPGA AI Suite IP Reference Manual
2. About the FPGA AI Suite IP
3. FPGA AI Suite IP Generation Utility
4. FPGA AI Suite Ahead-of-Time Splitter Utility
5. CSR Map and Descriptor Queue
A. FPGA AI Suite IP Reference Manual Archives
B. FPGA AI Suite IP Reference Manual Document Revision History

2.7. Feature Input and Output Streaming

The FPGA AI Suite can be configured to accept AXI-streaming (AXI4-Stream) input features, produce AXI-streaming (AXI4-Stream) output features, or both. When input streaming is enabled, graph inputs must fit entirely in the stream buffer. This section describes the interfaces and operation of the input and output streaming modes. The available modes of operation for DDR-free (discussed in DDR-Free Operation) and DDR-enabled designs are summarized in the following table:
Table 8.  Summary of Streaming Operation Modes
Input Mode Output Mode Description
DDR-free supported configurations
Streaming Streaming The only supported mode of operation when external memory is not available. Useful for data processing pipelines where pre- and post- processing stages are on the FPGA device and have AXI-streaming interfaces. Does not support CPU subgraphs or sliced inputs (stream buffer must be large enough to stage the entire input).
DDR-enabled supported configurations
Streaming Streaming For data processing pipelines where pre- and post- processing stages are on the FPGA device and have AXI-streaming interfaces. Does not support sliced inputs.
DDR-memory Streaming For pipelines where the host CPU is the data source, and post-processing stages are on the FPGA device with an AXI-streaming interface. Supports CPU subgraphs and sliced inputs.
Streaming DDR-memory For pipelines where the data source or pre-processing stage is an AXI-streaming IP, and the output should go to the CPU host for post-processing. Does not support sliced inputs.
DDR-memory DDR-memory For applications where the host CPU is the data source and sink. Supports CPU subgraphs and sliced inputs.
When input and output streaming is enabled, the system architecture can be described as shown in the following diagram:
Figure 7.  FPGA AI Suite IP with Input and Output Streaming


For more information about the configuration and operation of these streaming interfaces, refer to the following sections:

Section Content
Input Streaming
Output Streaming

Level Two Title