FPGA AI Suite: IP Reference Manual

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ID 768974
Date 3/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite IP Reference Manual 2. About the FPGA AI Suite IP 3. FPGA AI Suite IP Generation Utility 4. FPGA AI Suite Ahead-of-Time Splitter Utility 5. CSR Map and Descriptor Queue A. FPGA AI Suite IP Reference Manual Archives B. FPGA AI Suite IP Reference Manual Document Revision History
2. About the FPGA AI Suite IP x
2.1. Supported Models 2.2. Model Performance 2.3. FPGA AI Suite Layer / Primitive Ranges 2.4. FPGA AI Suite IP Block Configuration 2.5. IP Block Interfaces
2.1. Supported Models x
2.1.1. MobileNet V2 differences between Caffe and TensorFlow models
2.2. Model Performance x
2.2.1. Throughput on the MobileNetV1 model (and other very fast models)
2.4. FPGA AI Suite IP Block Configuration x
2.4.1. Architecture Description File Format for Instance Parameterization 2.4.2. Architecture Description File Parameters
2.4.2. Architecture Description File Parameters x
2.4.2.1. Parameter Group: Global Parameters 2.4.2.2. Parameter Group: activation 2.4.2.3. Parameter Group: pe_array 2.4.2.4. Parameter Group: pool 2.4.2.5. Parameter Group: depthwise 2.4.2.6. Module: softmax 2.4.2.7. Parameter Group: dma 2.4.2.8. Parameter Group: xbar 2.4.2.9. Parameter Group: filter_scratchpad 2.4.2.10. Parameter Group: config_network 2.4.2.11. (Early Access) Parameter Group: layout_transform_params Parameter: layout_transform_params/data_element_width Parameters: layout_transform_params/channels, layout_transform_params/feature_height, layout_transform_params/feature_width, layout_transform_params/feature_depth, layout_transform_params/stride_height, layout_transform_params/stride_width, layout_transform_params/stride_depth, layout_transform_params/pad_top, layout_transform_params/pad_left, layout_transform_params/pad_depth, layout_transform_params/output_channels, layout_transform_params/output_height, layout_transform_params/output_width, layout_transform_params/output_depth
2.5. IP Block Interfaces x
2.5.1. Clock and Reset 2.5.2. AXI Interfaces 2.5.3. AXI Interface Clock and Reset 2.5.4. Input Feature Tensor In-Memory Format 2.5.5. Output Tensor In-Memory Format
2.5.4. Input Feature Tensor In-Memory Format x
2.5.4.1. Multiple Input Graphs 2.5.4.2. Input Folding 2.5.4.3. Input Scale and Shift 2.5.4.4. Input Transform Mapping 2.5.4.5. Input Layout Transform Hardware
3. FPGA AI Suite IP Generation Utility x
3.1. IP Generation Utility Execution Flows 3.2. IP Generation Utility Inputs 3.3. IP Generation Utility Outputs 3.4. IP Generation Utility Command Line Options
3.4. IP Generation Utility Command Line Options x
3.4.1. The --flow create_ip Flow 3.4.2. The --flow add_arch Flow 3.4.3. The --flow list Flow 3.4.4. The --flow remove_arch Flow
4. FPGA AI Suite Ahead-of-Time Splitter Utility x
4.1. Files Generated by the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.2. Building the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.3. Running the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.4. FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility Example Application
5. CSR Map and Descriptor Queue x
5.1. Discovery ROM 5.2. Interrupt Control 5.3. DMA Descriptor Queue 5.4. DMA Control Registers 5.5. Performance Registers 5.6. Debug Network Registers 5.7. DMA License Register
1. FPGA AI Suite IP Reference Manual
2. About the FPGA AI Suite IP
3. FPGA AI Suite IP Generation Utility
4. FPGA AI Suite Ahead-of-Time Splitter Utility
5. CSR Map and Descriptor Queue
A. FPGA AI Suite IP Reference Manual Archives
B. FPGA AI Suite IP Reference Manual Document Revision History

2.4.2.11. (Early Access) Parameter Group: layout_transform_params

These parameters configure the input tensor layout transformation module of the FPGA AI Suite IP.

Early access only: This feature has early access support only for FPGA AI Suite 2024.1. Full support for this feature is planned for a future release.

Parameter: layout_transform_params/data_element_width

This parameter sets the width of the input values. The layout transform hardware supports U8 or FP16 inputs only.

Legal values:
[8, 16]

Parameters: layout_transform_params/channels, layout_transform_params/feature_height, layout_transform_params/feature_width, layout_transform_params/feature_depth, layout_transform_params/stride_height, layout_transform_params/stride_width, layout_transform_params/stride_depth, layout_transform_params/pad_top, layout_transform_params/pad_left, layout_transform_params/pad_depth, layout_transform_params/output_channels, layout_transform_params/output_height, layout_transform_params/output_width, layout_transform_params/output_depth

This group configures the range of feature shapes, padding, and convolution strides that the layout transform hardware module supports.
Early access restriction: In the early access release of this feature, these values must be set to exactly match the parameters of the ML model's first convolution instruction. In a future release of FPGA AI Suite, the values in this configuration represent the maximum (rather than exact) values, for greater flexibility.

To perform the input tensor format transformation and folding operations in hardware, the feature dimensions, along with the stride and padding values of the first convolution operation in the model, are required. Folded output dimensions are also required where folding refers to the process of moving values from the input tensor that are part of the same convolution filter stride into the channel dimension to increase efficiency in the PE array as described in Input Folding.

The folded output dimensions are derived from the input tensor according to the following relations:

For more information about the input tensor layout transform, refer to Input Feature Tensor In-Memory Format.

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