FPGA AI Suite: Compiler Reference Manual

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ID 768972
Date 3/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite Compiler Reference Manual 2. About the FPGA AI Suite Compiler 3. FPGA AI Suite Compiler Use Modes 4. FPGA AI Suite Compiler Command Line Options A. FPGA AI Suite Compiler Reference Manual Archives B. FPGA AI Suite Compiler Reference Manual Document Revision History
3. FPGA AI Suite Compiler Use Modes x
3.1. Compiling a Graph 3.2. Estimating the Performance of a Graph 3.3. Estimating the Performance of a Partition of a Graph 3.4. Estimating the Area of an Architecture 3.5. Generating an Optimized Architecture
3.5. Generating an Optimized Architecture x
3.5.1. Generating an Architecture for Highest Performance 3.5.2. Generating an Architecture Optimized for a Frame Rate Target Value
4. FPGA AI Suite Compiler Command Line Options x
4.1. Inputs (dla_compiler Command Options) 4.2. Outputs (dla_compiler Command Options) 4.3. Reporting (dla_compiler Command Options) 4.4. Compilation Options (dla_compiler Command Options) 4.5. Architecture Options (dla_compiler Command Options) 4.6. Architecture Optimizer Options (dla_compiler Command Options) 4.7. Analyzer Tool Options (dla_compiler Command Options) 4.8. Miscellaneous Options (dla_compiler Command Options) 4.9. Input File Formats for dla_compiler Command 4.10. Generation of Output File Formats 4.11. The Partitioning Table Report
1. FPGA AI Suite Compiler Reference Manual
2. About the FPGA AI Suite Compiler
3. FPGA AI Suite Compiler Use Modes
4. FPGA AI Suite Compiler Command Line Options
A. FPGA AI Suite Compiler Reference Manual Archives
B. FPGA AI Suite Compiler Reference Manual Document Revision History

2. About the FPGA AI Suite Compiler

The FPGA AI Suite compiler (the dla_compiler command) is built on the OpenVINO™ framework. The compiler for a specific release of the FPGA AI Suite depends on a specific OpenVINO™ version. For details, review the I Getting Started Guide.

In the FPGA AI Suite, the compiler does the following tasks:

  • Generates optimized FPGA AI Suite architecture configurations suitable for executing a given set of OpenVINO™ graphs within specified system constraints.
  • Estimates the performance of an OpenVINO™ graph on a given Intel® FPGA AI Suite architecture.
  • Estimates the FPGA resource requirements for a given parameterization of the IP.
  • Produces compiled binaries of OpenVINO™ graphs suitable for execution on a given FPGA AI Suite architecture.
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