Intel® FPGA AI Suite: Getting Started Guide

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ID 768970
Date 2/02/2024
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite Getting Started Guide 2. Intel® FPGA AI Suite Components 3. Intel® FPGA AI Suite Installation Overview 4. Installing the Intel® FPGA AI Suite Compiler and IP Generation Tools 5. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites 6. Intel® FPGA AI Suite Quick Start Tutorial A. Intel® FPGA AI Suite Getting Started Guide Archives B. Intel® FPGA AI Suite Getting Started Guide Document Revision History
3. Intel® FPGA AI Suite Installation Overview x
3.1. Intel® FPGA AI Suite Directory Structure
4. Installing the Intel® FPGA AI Suite Compiler and IP Generation Tools x
4.1. Supported FPGA Families 4.2. Operating System Prerequisites 4.3. Installing the Intel® FPGA AI Suite With System Package Management Tools 4.4. Installing OpenVINO™ Toolkit 4.5. Installing Intel® Quartus® Prime Pro Edition Software 4.6. Setting Required Environment Variables 4.7. Installing Intel® Threading Building Blocks (TBB) 4.8. Finalizing Your Intel® FPGA AI Suite Installation
4.3. Installing the Intel® FPGA AI Suite With System Package Management Tools x
4.3.1. Installing the Intel® FPGA AI Suite Into an Alternative Location
5. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites x
5.1. PCIe-based Design Example Hardware Prerequisites 5.2. PCIe-based Design Example Operating System Prerequisites 5.3. PCIe-based Design Example Software Prerequisites
5.3. PCIe-based Design Example Software Prerequisites x
5.3.1. Additional Software Prerequisites for the PCIe-based Design Example for Intel Agilex® 7 Devices 5.3.2. Additional Software Prerequisites for the PCIe-Based Design Example for Intel® Arria® 10 Devices Intel® Acceleration Stack Installation Summary Intel® Acceleration Stack Environment Settings for Design Example Bitstream Generation Requirements
6. Intel® FPGA AI Suite Quick Start Tutorial x
6.1. Creating a Working Directory 6.2. Preparing OpenVINO™ Model Zoo 6.3. Preparing a Model 6.4. Running the Graph Compiler 6.5. Preparing an Image Set 6.6. Programming the FPGA Device 6.7. Performing Inference on the PCIe-Based Example Design 6.8. Building an FPGA Bitstream for the PCIe Example Design 6.9. Building the Example FPGA Bitstreams 6.10. Preparing a ResNet50 v1 Model 6.11. Performing Inference on the Inflated 3D (I3D) Graph 6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics
6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics x
6.12.1. Preparing a YOLOv3 Model 6.12.2. Preparing a COCO Validation Dataset and Annotations 6.12.3. Inference on YOLOv3 and Calculating Accuracy Scores
1. Intel® FPGA AI Suite Getting Started Guide
2. Intel® FPGA AI Suite Components
3. Intel® FPGA AI Suite Installation Overview
4. Installing the Intel® FPGA AI Suite Compiler and IP Generation Tools
5. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites
6. Intel® FPGA AI Suite Quick Start Tutorial
A. Intel® FPGA AI Suite Getting Started Guide Archives
B. Intel® FPGA AI Suite Getting Started Guide Document Revision History

5.3.2. Additional Software Prerequisites for the PCIe-Based Design Example for Intel® Arria® 10 Devices

The Intel® PAC with Intel® Arria® 10 GX FPGA board used by the PCIe-based design example for Intel® Arria® 10 devices adds the following additional software prerequisites:

  • Linux kernel version 4.15

    This kernel is provided in Ubuntu* 18.04.1, which is listed as the operating system prerequisite for the PCIe-based design example for Intel® Arria® 10 devices in PCIe-based Design Example for Intel Arria 10 Operating System Prerequisites.

  • Intel® Acceleration Stack for Development Version 1.2.1 (includes Intel® Quartus® Prime Pro Edition Version 19.2)
  • Intel® Quartus® Prime Pro Edition Version 19.2

    This software is needed only if you plan to create bitstreams that correspond to customized Intel® FPGA AI Suite IP instances.

The Intel® Acceleration Stack includes a version of Intel® Quartus® Prime Pro Edition Version 19.2 that does not require a license.

Download the Intel® Acceleration Stack Version 1.2.1 from FPGA Development tab at the following URL: https://www.intel.com/content/www/us/en/software-kit/665840/intel-pac-with-intel-arria-10-gx-fpga-acceleration-stack-version-1-2-1.html.

Ensure that you are downloading a10_gx_pac_ias_1_2_1_pv_dev.tar.gz. The download should be approximately 1.1GB.

For installation instructions, see "Installing the Intel® Acceleration Stack Development Package on the Host Machine" in Intel® Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA .

Important: After you install the Intel® Acceleration Stack, reboot your system so that the Intel® PAC with Intel® Arria® 10 GX FPGA board can be detected by the lspci command.

Intel® Acceleration Stack Installation Summary

The following commands install a version of the stack that is suitable for use with the PCIe-based example design for Intel® Arria® 10 devices on Ubuntu* 18.04.1: 
tar zxf a10_gx_pac_ias_1_2_1_pv_dev.tar.gz
cd a10_gx_pac_ias_1_2_1_pv_dev_installer
./setup.sh
Warning: The installation script asks for sudo permission early in the process and might ask for sudo permission again near the end of the process. If you do not monitor the installation, the sudo command times out and you need to repeat the installation.
During the installation, some prompts ask you about optional features. Answer them as follows:
  • Do you wish to install the OPAE?

    Yes

  • Do you wish to install OPAE PACsign package?

    Yes

  • Accept the license and choose the install directory

    The recommendation is to use default directory.

  • After the Intel® Acceleration Stack I installation finishes, the installer installs Intel® Quartus® Prime Pro Edition. Choose the Intel® Quartus® Prime installation directory

    The recommendation is to use the default directory.

Intel® Acceleration Stack Environment Settings for Design Example

Each time before you use the PCIe-based design example for Intel® Arria® 10 devices, run the following commands: 
export OPAE_SDK_ROOT=/usr/
source /home/$USER/inteldevstack/init_env.sh

Consider adding these commands to your .bashrc file.

If you did not install the Intel® Acceleration Stack into the default location, then adjust these commands to reflect your installation location.

The first time that you the source init_env.sh command, you might need to use a root shell.

The init_env.sh script configures huge pages and sets permissions so that the fpgaconf command does not need to use the sudo command later. If the init_env.sh script fails, you might see errors when the runtime initializes DMA or when programming the FPGA AFU bitstream (the partial reconfiguration region).

Bitstream Generation Requirements

If you plan to create bitstreams that correspond to custom Intel® FPGA AI Suite IP instances (or want to create your own bitstreams), then add the Platform Designer command (qsys) to your PATH environment variable. Add the following commands into your .bashrc file, and adjust the paths depending on your installation locations if needed: 
PATH="$PATH:/opt/intelFPGA_pro/quartus_19.2.0b57/qsys/bin/"
PATH="$PATH:/opt/intelFPGA_pro/quartus_19.2.0b57/quartus/bin/"
export PATH

After you successfully install the board, continue by installing the compiler and IP generation tool as described in Installing the Intel FPGA AI Suite Compiler and IP Generation Tools.

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