Intel® FPGA AI Suite: Getting Started Guide

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ID 768970
Date 4/05/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite Getting Started Guide 2. About the Intel® FPGA AI Suite 3. Installing the Intel® FPGA AI Suite 4. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites 5. Installing the Intel FPGA AI Suite Compiler and IP Generation Tools 6. Intel® FPGA AI Suite Quick Start Tutorial A. Installation Notes for Other Operating Systems B. Intel® FPGA AI Suite Getting Started Guide Archives C. Intel® FPGA AI Suite Getting Started Guide Document Revision History
3. Installing the Intel® FPGA AI Suite x
3.1. Intel® FPGA AI Suite Directory Structure
4. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites x
4.1. PCIe-based Design Example Hardware Prerequisites 4.2. PCIe-based Design Example Operating System Prerequisites 4.3. PCIe-based Design Example Software Prerequisites
4.3. PCIe-based Design Example Software Prerequisites x
4.3.1. Additional Software Prerequisites for the PCIe-based Design Example for Intel Agilex® 7 Devices 4.3.2. Additional Software Prerequisites for the PCIe-Based Design Example for Intel® Arria® 10 Devices
5. Installing the Intel FPGA AI Suite Compiler and IP Generation Tools x
5.1. Supported FPGA Families 5.2. Operating System Prerequisites 5.3. Software Prerequisites 5.4. Installing the Intel® FPGA AI Suite Using System Package Management Tools 5.5. Installing the Intel® FPGA AI Suite Into an Alternative Location
5.3. Software Prerequisites x
5.3.1. OpenVINO™ Toolkit 5.3.2. Intel® Quartus® Prime Pro Edition Software
6. Intel® FPGA AI Suite Quick Start Tutorial x
6.1. Creating a Working Directory 6.2. Preparing OpenVINO™ Model Zoo and Model Optimizer 6.3. Preparing a Model 6.4. Running the Graph Compiler 6.5. Preparing an Image Set 6.6. Programming the FPGA Device 6.7. Performing Inference on the PCIe-Based Example Design 6.8. Building an FPGA Bitstream for the PCIe Example Design 6.9. Building the Example FPGA Bitstreams 6.10. Preparing a ResNet50 v1 Model 6.11. Performing Inference on the Inflated 3D (I3D) Graph 6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics
6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics x
6.12.1. Preparing a YOLOv3 Model 6.12.2. Preparing a COCO Validation Dataset and Annotations 6.12.3. Inference on YOLOv3 and Calculating Accuracy Scores
A. Installation Notes for Other Operating Systems x
A.1. CentOS* 7 Installation Notes
1. Intel® FPGA AI Suite Getting Started Guide
2. About the Intel® FPGA AI Suite
3. Installing the Intel® FPGA AI Suite
4. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites
5. Installing the Intel FPGA AI Suite Compiler and IP Generation Tools
6. Intel® FPGA AI Suite Quick Start Tutorial
A. Installation Notes for Other Operating Systems
B. Intel® FPGA AI Suite Getting Started Guide Archives
C. Intel® FPGA AI Suite Getting Started Guide Document Revision History

6.8. Building an FPGA Bitstream for the PCIe Example Design

To complete this portion of the tutorial, you must meet the following prerequisites:
  • You must have a license for bitstream generation of the Intel® FPGA AI Suite IP.
  • You must have a specific version of Intel® Quartus® Prime Pro Edition installed:
    • The PCIe-based design example for Intel® Arria® 10 requires Intel® Quartus® Prime Pro Edition Version 19.2.
    • The PCIe-based design example for Intel Agilex® 7 devices requires Intel® Quartus® Prime Pro Edition Version 22.4.
  • You must have the following paths included in your $PATH environment variable:
    • quartus/bin
    • qsys/bin

If you do not have a license for Intel® FPGA AI Suite, the generated IP has a built-in inference-count limitation. Any inference operations that occur after the limit is reached generate an error message that indicates that a license is required. To reset the inference count limit, you must reprogram the bitstream onto the FPGA device.

Building an FPGA Bitstream for the PCIe-Based Design Example for Intel® Arria® 10 Devices

Run the following command for the PCIe-Based Design Example for Intel® Arria® 10 devices: 
cd $COREDLA_WORK/demo
dla_build_example_design.py \
  -a $COREDLA_ROOT/example_architectures/A10_Performance.arch \
  --build -ed 1 \
  --build-dir build_A10_Performance \
  --output-dir $COREDLA_WORK/demo/my_bitstreams

You must include the -n 1 option when you build the A10_FP16_Example.arch architecture because the FPGA device on the Intel® PAC with Intel® Arria® 10 GX FPGA has enough DSPs only to build a single instance of this architecture.

If you want to vary the Intel® Quartus® Prime random seed, specify the --seed option as part of the dla_build_example_design.py command.

If you want to see the full set of supported options, run the following command: 
dla_build_example_design.py --help

This commands places the bitstreams into the my_bitstreams directory. The bitstream is named A10_Performance.gbs.

After the bitstream is built, you must program it onto the FPGA following the instructions in section Programming the FPGA Device.

Building an FPGA Bitstream for the PCIe-Based Design Example for Intel Agilex® 7 Devices

Run the following command for the PCIe-Based Design Example for Intel Agilex® 7 devices: 
cd $COREDLA_WORK/demo
dla_build_example_design.py \  
  -a $COREDLA_ROOT/example_architectures/AGX7_Performance.arch \
  --build -ed 3 -n 4 \
  --build-dir build_AGX7_Performance \
  --output-dir $COREDLA_WORK/demo/my_bitstreams

If the AOCL_BOARD_PACKAGE_ROOT environment variable is not set, the dla_build_example_design.py command returns an error message. To set this environment variable, review the instructions in Additional Software Prerequisites for the PCIe-based Design Example for Intel Agilex 7 Devices.

If you want to see the full set of supported options, run the following command: 
dla_build_example_design.py --help
The dla_build_example_design.py command provides a --seed option that you can use to vary the Intel® Quartus® Prime random seed.

This commands places the bitstreams into the my_bitstreams directory. The bitstream is named AGX7_Performance.sof.

After the bitstream is built, you must program it onto the FPGA following the instructions in section Programming the FPGA Device.

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