Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Network-on-Chip (NoC) Overview 2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs 3. NoC Design Flow in Intel® Quartus® Prime Pro Edition 4. NoC Real-time Performance Monitoring 5. Simulating NoC Designs 6. NoC Power Estimation 7. Hard Memory NoC IP Reference 8. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
1. Network-on-Chip (NoC) Overview x
1.1. Introduction to Intel Agilex® 7 M-Series FPGAs 1.2. Terminology for Intel Agilex® 7 M-Series FPGAs 1.3. General NoC Architecture and Applications
1.3. General NoC Architecture and Applications x
1.3.1. General NoC Architecture 1.3.2. Example NoC Applications
1.3.2. Example NoC Applications x
1.3.2.1. Parallel Computing NoC Application 1.3.2.2. SmartNIC NoC Application
2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs x
2.1. High-Level Architecture 2.2. NoC Segments 2.3. NoC Switch and Link Detail 2.4. Fabric NoC 2.5. NoC Protocol Support 2.6. NoC Design Considerations
2.2. NoC Segments x
2.2.1. UIB Segments 2.2.2. GPIO-B Segments 2.2.3. GPIO-B and HPS Segment 2.2.4. SDM Segment 2.2.5. PLL and SSM Segment
2.5. NoC Protocol Support x
2.5.1. AXI4 Protocol Support 2.5.2. AXI4 Handshaking Support 2.5.3. Quality of Service (QoS) Support 2.5.4. Transaction Ordering Support 2.5.5. AXI4-Lite Protocol Support
2.6. NoC Design Considerations x
2.6.1. Determining the Number of NoC Targets 2.6.2. Determining the Number of NoC Initiators 2.6.3. Fabric NoC Considerations 2.6.4. Latency Considerations 2.6.5. Initiator and Target Bandwidth Considerations 2.6.6. Horizontal Bandwidth Considerations 2.6.7. GPIO-B Bypass Mode and Initiators
3. NoC Design Flow in Intel® Quartus® Prime Pro Edition x
3.1. Hard Memory NoC Design Flow Overview 3.2. Using NoC Example Designs 3.3. NoC Building Blocks 3.4. Connecting NoC IP 3.5. Making NoC Logical Assignments 3.6. Making NoC Physical Assignments Using Interface Planner 3.7. Compiling the NoC Design
3.1. Hard Memory NoC Design Flow Overview x
3.1.1. NoC Design Flow Options
3.3. NoC Building Blocks x
3.3.1. NoC Initiators for Hard Processor Systems 3.3.2. NoC Targets for Hard Processor Systems 3.3.3. NoC Initiators for Fabric AXI4 Managers 3.3.4. NoC Targets for Fabric AXI4 Managers 3.3.5. NoC Clock Control
3.4. Connecting NoC IP x
3.4.1. General NoC IP Connectivity Guidelines 3.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 3.4.4. Connectivity Guidelines: NoC Clock Control 3.4.5. Connectivity Guidelines: NoC Initiators for HPS 3.4.6. Connectivity Guidelines: NoC Targets for HPS
3.4.1. General NoC IP Connectivity Guidelines x
3.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 3.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
3.5. Making NoC Logical Assignments x
3.5.1. Creating NoC Assignments for Compilation 3.5.2. Using the NoC Assignment Editor 3.5.3. Troubleshooting NoC Assignment Editor 3.5.4. NoC Connection and Addressing Examples
3.5.2. Using the NoC Assignment Editor x
3.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 3.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 3.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 3.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
3.5.4. NoC Connection and Addressing Examples x
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator 3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator 3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator 3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator 3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator x
3.5.4.1.1. Example 1: Platform Designer Connection Flow 3.5.4.1.2. Example 1: NoC Assignment Editor Connection Flow
3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator x
3.5.4.2.1. Example 2: Platform Designer Connection Flow 3.5.4.2.2. Example 2: NoC Assignment Editor Connection Flow
3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator x
3.5.4.3.1. Example 3: Platform Designer Connection Flow 3.5.4.3.2. Example 3: NoC Assignment Editor Connection Flow
3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator x
3.5.4.4.1. Example 4: Platform Designer Connection Flow 3.5.4.4.2. Example 4: NoC Assignment Editor Connection Flow
3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces x
3.5.4.5.1. Example 5: Platform Designer Connection Flow 3.5.4.5.2. Example 5: NoC Assignment Editor Connection Flow
3.6. Making NoC Physical Assignments Using Interface Planner x
3.6.1. Using Interface Planner 3.6.2. Recommended Placement Order for NoC Elements in Interface Planner 3.6.3. Hard Memory NoC Locations in Interface Planner 3.6.4. NoC Performance Reports in Interface Planner
3.7. Compiling the NoC Design x
3.7.1. Fitter NoC Reports 3.7.2. Viewing NoC Elements in Chip Planner
5. Simulating NoC Designs x
5.1. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 5.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 5.3. Contents of Simulation Registration Include File
6. NoC Power Estimation x
6.1. Using the Intel FPGA PTC to Estimate NoC Power
7. Hard Memory NoC IP Reference x
7.1. NoC Initiator Intel FPGA IP 7.2. NoC Clock Control Intel FPGA IP
7.1. NoC Initiator Intel FPGA IP x
7.1.1. NoC Initiator Intel FPGA IP Parameters 7.1.2. NoC Initiator Intel FPGA IP Interfaces
7.1.2. NoC Initiator Intel FPGA IP Interfaces x
7.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces 7.1.2.2. NoC Initiator AXI4 User Interface Signals 7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals 7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 7.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
7.2. NoC Clock Control Intel FPGA IP x
7.2.1. NoC Clock Control Intel FPGA IP Parameters 7.2.2. NoC Clock Control Intel FPGA IP Interfaces 7.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
Answers to Top FAQs
1. Network-on-Chip (NoC) Overview
2. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
3. NoC Design Flow in Intel® Quartus® Prime Pro Edition
4. NoC Real-time Performance Monitoring
5. Simulating NoC Designs
6. NoC Power Estimation
7. Hard Memory NoC IP Reference
8. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals

There are three types of AXI4-Lite interfaces that you may have in your design:

  1. The NoC subsystem uses an AXI4-Lite target that you can access to read performance monitoring registers.
  2. The HBM2e IP optionally uses an AXI4-Lite target that provides access to the HBM2e memory controller's configuration and status registers.
  3. The EMIF IP uses a AXI4-Lite target that connects to the I/O subsystem (IOSSM) and provides the following functionality:
    • Through the IOSSM Mailbox, provides access to the HMC (hard memory controller) CSRs.
    • Through the IOSSM Mailbox, provides capability for discovery (which EMIF ID is in the same GPIO-B bank as this IOSSM).
    • Through the IOSSM Mailbox, provides API to read calibration diagnostic info.
    • Through the IOSSM Mailbox, provides API to read PLL lock status.
    • Provides direct access to (reading from or writing to) PHY registers.

The AXI4-Lite interface is primarily for relatively low-bandwidth sideband operations. Conversely, the AXI4 interface is primarily for high-bandwidth, mainband operations.

The signals that this section describes refer to signal names that correspond to an AXI4-Lite interface. These signals adopt the prefix s<x>_axi4lite_, for example s0_axi4lite_awaddr.

Table 20.  AXI4-Lite Write Address (AW) command Channel
Port Name Width Direction Description
<prefix>_awaddr 44 Input Write Address. The write address gives the address of the first transfer in a write burst transaction.
<prefix>_awprot 3 Input

Protection Type [reserved for future use]. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.

3’b0101 = Unprivileged, non-secure data access

<prefix>_awvalid 1 Input Write Address Valid. This signal indicates that the manager is signaling valid write address and control information. The write address valid signal must not be dependent on the write address ready signal.
<prefix>_awready 1 Output Write Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
Table 21.  AXI4-Lite Write Data (W) Channel
Port Name Width Direction Description
<prefix>_wdata 32 Input Write Data.
<prefix>_wstrb 4 Input Write Strobes (Byte Enables). These signals indicate which bytes of the AXI4-Lite wdata signal hold valid data. There is one byte strobe for every eight bits of write data.
<prefix>_wvalid 1 Input Write Valid. This signal indicates that valid write data and write strobes are available. The write address valid signal must not be dependent on the write address ready signal.
<prefix>_wready 1 Output Write Ready. This signal indicates that the subordinate can accept write data.
Table 22.  AXI4-Lite Write Response (B) Channel
Port Name Width Direction Description
<prefix>_bresp 2 Output

Write Response. This signal indicates the status of the write transaction.

  • 2’b00 = OKAY; indicates that normal access is successful.
  • 2’b10 = SLVERR; an unsuccessful transaction.
  • 2'b11 = DECERR; indicates that the hard memory NoC could not extract a valid destination address from the address supplied in the original write command. Note: 2'b01 = EXOKAY is not returned as implementation does not support exclusive access.
<prefix>_bvalid 1 Output Write Response Valid. This signal indicates that the host or manager is signaling a valid write response.
<prefix>_bready 1 Input Response Ready. This signal indicates that the manager can accept a write response.
Table 23.  AXI4-Lite Read Address (AR) command Channel
Port Name Width Direction Description
<prefix>_araddr 44 Input Read Address. The read address gives the address of the first transfer in a read burst transaction.
<prefix>_arprot 3 Input

Protection Type [reserved for future use]. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.

3’b010 = Unprivileged, non-secure data access

<prefix>_arvalid 1 Input Read Address Valid. This signal indicates that the host or manager is signaling valid write address and control information. The read address valid signal must not be dependent on the read address ready signal.
<prefix>_arready 1 Output Read Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
Table 24.  AXI4-Lite Read Data (R) Channel
Port Name Width Direction Description
<prefix>_rdata 32 Output Read Data.
<prefix>_rresp 2 Output

Read Response. This signal indicates the status of the read transfer:

  • 2’b00 = OKAY
  • 2’b10 = SLVERR: indicates an unsuccessful transaction.
  • 2'b11 = DECERR; indicates that the hard memory NoC could not extract a valid destination address from the address supplied in the original read command. Note that 2'b01 = EXOKAY is not returned as implementation does not support exclusive access.
<prefix>_rvalid 1 Output Read Valid. This signal indicates that the subordinate is signaling the required read data.
<prefix>_rready 1 Input Read Ready. This signal indicates that the manager can accept the read data and response information.
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