Intel Agilex® 7 LVDS SERDES User Guide: M-Series

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ID 768615
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 M-Series LVDS SERDES Overview 2. Intel Agilex® 7 M-Series LVDS SERDES Architecture 3. Intel Agilex® 7 M-Series LVDS SERDES Transmitter 4. Intel Agilex® 7 M-Series LVDS SERDES Receiver 5. Intel Agilex® 7 M-Series High-Speed LVDS I/O Implementation Guide 6. Intel Agilex® 7 M-Series LVDS SERDES Timing 7. LVDS SERDES Intel® FPGA IP Design Examples 8. Intel Agilex® 7 M-Series LVDS SERDES Design Guidelines 9. Intel Agilex® 7 M-Series LVDS SERDES Troubleshooting Guidelines 10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: M-Series 11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: M-Series
1. Intel Agilex® 7 M-Series LVDS SERDES Overview x
1.1. LVDS SERDES Usage Modes
2. Intel Agilex® 7 M-Series LVDS SERDES Architecture x
2.1. Intel Agilex® 7 M-Series GPIO-B Banks, SERDES, and DPA Locations 2.2. SERDES Blocks, Modes, and Clock Domains
3. Intel Agilex® 7 M-Series LVDS SERDES Transmitter x
3.1. LVDS SERDES Transmitter Blocks 3.2. Serializer 3.3. Clocking the Differential Transmitters
3.2. Serializer x
3.2.1. Serializer Bypass for DDR and SDR Operations 3.2.2. Differential I/O Bit Position
3.3. Clocking the Differential Transmitters x
3.3.1. Transmitter Output Clock Parameters Settings
3.3.1. Transmitter Output Clock Parameters Settings x
3.3.1.1. Edge-Aligned tx_outclock to tx_out
4. Intel Agilex® 7 M-Series LVDS SERDES Receiver x
4.1. LVDS SERDES Receiver Blocks 4.2. Clocking the LVDS SERDES Receivers 4.3. LVDS SERDES Receiver Modes
4.1. LVDS SERDES Receiver Blocks x
4.1.1. Dynamic Phase Alignment Block 4.1.2. Synchronizer (DPA FIFO) 4.1.3. Data Realignment Block (Bit Slip) 4.1.4. Deserializer
4.2. Clocking the LVDS SERDES Receivers x
4.2.1. Receiver Input Clock Parameters Settings
4.2.1. Receiver Input Clock Parameters Settings x
4.2.1.1. Edge-Aligned inclock to rx_in 4.2.1.2. Center-Aligned inclock to rx_in
4.3. LVDS SERDES Receiver Modes x
4.3.1. Non-DPA Mode 4.3.2. DPA Mode 4.3.3. Soft-CDR Mode
5. Intel Agilex® 7 M-Series High-Speed LVDS I/O Implementation Guide x
5.1. LVDS SERDES Intel® FPGA IP 5.2. LVDS Interface with External PLL Mode 5.3. LVDS SERDES IP Initialization and Reset
5.1. LVDS SERDES Intel® FPGA IP x
5.1.1. Release Information 5.1.2. LVDS SERDES Intel® FPGA IP Features 5.1.3. LVDS SERDES IP Usage Modes 5.1.4. Planning the LVDS Interface 5.1.5. Generating the LVDS SERDES Intel® FPGA IP 5.1.6. LVDS SERDES Intel® FPGA IP Parameter Settings 5.1.7. LVDS SERDES Intel® FPGA IP Signals
5.1.5. Generating the LVDS SERDES Intel® FPGA IP x
5.1.5.1. Intel® FPGA IP Generation Output
5.1.6. LVDS SERDES Intel® FPGA IP Parameter Settings x
5.1.6.1. LVDS SERDES Intel® FPGA IP General Settings 5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings 5.1.6.3. LVDS SERDES Intel® FPGA IP PLL Settings 5.1.6.4. LVDS SERDES Intel® FPGA IP Receiver Settings 5.1.6.5. LVDS SERDES Intel® FPGA IP Transmitter Settings 5.1.6.6. LVDS SERDES Intel® FPGA IP Clock Resource Summary
5.1.6.2. LVDS SERDES Intel® FPGA IP Pin Settings x
5.1.6.2.1. GPIO-B Pin Index Number and Respective Channel Pin Selection 5.1.6.2.2. Placing Channel Bytes in I/O Lanes 5.1.6.2.3. Locating the I/O Lane and Channel Pin through the Interface Planner
5.2. LVDS Interface with External PLL Mode x
5.2.1. IOPLL IP Signal Interface with LVDS SERDES IP 5.2.2. IOPLL Parameter Values for External PLL Mode 5.2.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
5.3. LVDS SERDES IP Initialization and Reset x
5.3.1. Initializing the LVDS SERDES IP in Non-DPA Mode 5.3.2. Initializing the LVDS SERDES IP in DPA Mode 5.3.3. Resetting the DPA 5.3.4. Word Boundaries Alignment Aligning with Control Characters Aligning without Control Characters
5.3.4. Word Boundaries Alignment x
Aligning with Control Characters Aligning without Control Characters 5.3.4.1. Aligning Word Boundaries
6. Intel Agilex® 7 M-Series LVDS SERDES Timing x
6.1. LVDS SERDES Intel® FPGA IP Timing 6.2. LVDS SERDES Source-Synchronous Timing Budget
6.1. LVDS SERDES Intel® FPGA IP Timing x
6.1.1. I/O Timing Analysis 6.1.2. FPGA Timing Analysis 6.1.3. Timing Analysis for the External PLL Mode
6.1.1. I/O Timing Analysis x
6.1.1.1. Obtaining RSKM Report 6.1.1.2. Obtaining TCCS Report
6.2. LVDS SERDES Source-Synchronous Timing Budget x
6.2.1. Transmitter Channel-to-Channel Skew 6.2.2. Receiver Skew Margin
7. LVDS SERDES Intel® FPGA IP Design Examples x
7.1. LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples 7.2. LVDS SERDES IP Simulation Design Example
8. Intel Agilex® 7 M-Series LVDS SERDES Design Guidelines x
8.1. Use PLLs in Integer PLL Mode for LVDS 8.2. Use High-Speed Clock from PLL to Clock SERDES Only 8.3. Pin Placement for Differential Channels 8.4. SERDES Pin Pairs for Soft-CDR Mode 8.5. Placing LVDS Transmitters and Receivers in the Same GPIO-B Sub-Bank 8.6. Sharing LVDS SERDES I/O Lane with Other Intel® FPGA IPs 8.7. VCCIO_PIO Power Scheme for LVDS SERDES
8.3. Pin Placement for Differential Channels x
8.3.1. I/O PLLs Driving LVDS Transmitter and Receiver Channels 8.3.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank
1. Intel Agilex® 7 M-Series LVDS SERDES Overview
2. Intel Agilex® 7 M-Series LVDS SERDES Architecture
3. Intel Agilex® 7 M-Series LVDS SERDES Transmitter
4. Intel Agilex® 7 M-Series LVDS SERDES Receiver
5. Intel Agilex® 7 M-Series High-Speed LVDS I/O Implementation Guide
6. Intel Agilex® 7 M-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel Agilex® 7 M-Series LVDS SERDES Design Guidelines
9. Intel Agilex® 7 M-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: M-Series
11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: M-Series

5.3.4. Word Boundaries Alignment

You can perform word boundaries alignment with or without control characters in your data stream. If there are no training patterns or control characters available in the serial bit stream to use for word alignment, Intel recommends that you use the non-DPA mode.

Aligning with Control Characters

By adding control characters in the data stream, your logic can search for a known pattern to align the word boundaries. You can compare the received data for each channel, and then pulse the rx_bitslip_ctrl signal as required until you receive the control character.

Note: Intel recommends that you set the bit slip rollover count to the deserialization factor or higher. This setting allows enough depth in the bit slip circuit to roll through an entire word, if required.

Aligning without Control Characters

Without control characters in the data stream, you need a deterministic relationship between the reference clock and the data. With the deterministic relationship, you can predict the word boundary using timing simulation or laboratory measurement. You can only use deterministic relationship in non-DPA mode.

The only way to ensure a deterministic relationship on the default word position in the SERDES when the device powers up, or anytime the PLL is reset, is to have a reference clock equal to the data rate divided by the deserialization factor. This is important because the PLL locks to the rising edge of the reference clock. If you have one rising edge on the reference clock per serial word received, the deserializer always starts at the same position.

For example, if the data rate is 800 Mbps and the deserialization factor is 8, the PLL requires a 100 MHz reference clock.

Using timing simulation, or lab measurements, monitor the parallel words received and determine how many pulses of the rx_bitslip_ctrl you require to set your word boundaries. You can create a simple state machine to apply the required number of pulses after you enter user mode or at any time after you reset the PLL.

Note: If you are using the DPA or soft-CDR modes, the word boundary is not deterministic. The initial training of the DPA allows it to move forward or backward in phase relative to the incoming serial data. Therefore, there can be a ±1 bit of variance in the serial bit where the DPA locks initially.

Section Content
Aligning Word Boundaries

Level Two Title