F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 3/31/2025
Public

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2.4. Performance and Resource Utilization

Table 3.  IP Core FPGA Resource Utilization for F-Tile Low Latency 50G Ethernet Intel® FPGA IP Lists the resources and expected performance for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP.

These results were obtained using the current version of the Quartus® Prime Pro Edition software.

  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus® Prime Fitter Report.
IP Variation ALMs Dedicated Logic Registers Block Memory Bits
F-Tile Low Latency 50G Ethernet 17,339 912,800 206,080