F-Tile Low Latency 50G Ethernet Intel® FPGA Soft-IP User Guide

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ID 758946
Date 5/10/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP User Guide 2. About this IP 3. Getting Started 4. F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP Parameters 5. Functional Description 6. Reset 7. Interfaces and Signal Descriptions 8. Control, Status, and Statistics Register Descriptions 9. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP User Guide
2. About this IP x
2.1. Release Information 2.2. Features 2.3. Device Family Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Compiling the Full Design and Programming the FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the F-tile Reference and System PLL Clocks Intel® FPGA IP 3.5.3. Placement Settings for the 50G Ethernet Intel FPGA IP Core
5. Functional Description x
5.1. F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP Functional Description 5.2. User Interface to Ethernet Transmission
5.1. F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP Functional Description x
5.1.1. F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP TX MAC Datapath 5.1.2. 50 GbE TX PCS 5.1.3. F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP Core RX MAC Datapath 5.1.4. Link Fault Signaling Interface 5.1.5. 50 GbE RX PCS 5.1.6. Flow Control
5.1.1. F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP TX MAC Datapath x
5.1.1.1. Frame Padding 5.1.1.2. Preamble Insertion 5.1.1.3. Inter-Packet Gap Generation and Insertion 5.1.1.4. Frame Check Sequence (CRC32) Insertion
5.1.3. F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP Core RX MAC Datapath x
5.1.3.1. IP Core Preamble Processing 5.1.3.2. IP Core Malformed Packet Handling 5.1.3.3. Length/Type Field Processing
5.1.3.3. Length/Type Field Processing x
5.1.3.3.1. Length Checking 5.1.3.3.2. RX CRC Checking and Dynamic Forwarding
5.1.6. Flow Control x
5.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 5.1.6.2. XON/XOFF Pause Frames
5.2. User Interface to Ethernet Transmission x
5.2.1. Order of Transmission 5.2.2. Bit Order For TX and RX Datapaths
7. Interfaces and Signal Descriptions x
7.1. TX MAC Interface to User Logic 7.2. RX MAC Interface to User Logic 7.3. Transceivers 7.4. Transceiver Reconfiguration Signals 7.5. Avalon® Memory-Mapped Management Interface 7.6. Miscellaneous Status and Debug Signals 7.7. Flow Control Signals 7.8. Clock Signals 7.9. Reset Signals
8. Control, Status, and Statistics Register Descriptions x
8.1. TX MAC Registers 8.2. RX MAC Registers 8.3. Pause/PFC Flow Control Registers 8.4. Statistics Registers 8.5. Hard IP Registers
8.4. Statistics Registers x
8.4.1. Statistics Registers
1. About the F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel FPGA Soft-IP User Guide

8.1. TX MAC Registers

Table 21.  TX MAC Registers
Addr Name Description Reset Access
0x400 TXMAC_REVID

TX MAC revision ID for 50G TX MAC CSRs.

0x2007 2022

 RO
0x401 TXMAC_SCRATCH Scratch register available for testing. 0x0000 0000 RW
0x402 TXMAC_NAME_0

First 4 characters of IP core variation identifier string, "50gMACTxCSR".

 0x3235 674D

RO
0x403 TXMAC_NAME_1

Next 4 characters of IP core variation identifier string, "ACTx".

0x4143 5478

RO
0x404 TXMAC_NAME_2 Final 4 characters of IP core variation identifier string, "0CSR". The "0" is unprintable. 0x0043 5352

RO
0x405 LINK_FAULT

Link Fault Configuration Register. The following bits are defined:

  • Force Remote Fault bit[3]: When link fault generation is enabled, stops data transmission and forces transmission of a remote fault.
  • Disable Remote Fault bit[2]: When both link fault reporting and unidirectional transport are enabled, the core transmits data and does not transmit remote faults (RF). This bit takes effect when the value of this register is 28'hX4'b0111.
  • Unidir Enable bit[1]: When asserted, the core includes Clause 66 support for the remote link fault reporting on the Ethernet link.
  • Link Fault Reporting Enable bit[0]: The following encodings are defined:
    • 1'b1: The PCS generates the proper fault sequence on Ethernet link, when conditions are met.
    • 1'b0: The PCS does not generate the fault sequence.
28'hX_4'b0001 1

RW
0x407 MAX_TX_SIZE_CONFIG Specifies the maximum TX frame length. Frames that are longer are considered oversized. They are transmitted, but also increment the CNTR_TX_OVERSIZE register.

Bits [31:16] of this register are Reserved.

0xXXXX 2580 1

RW
0x40A TXMAC_CONTROL TX MAC Control Register. A single bit is defined:
  • Bit[1]: VLAN detection disabled. This bit is deasserted by default, implying VLAN detection is enabled.
30'hX2'b0X 1 RW
1 X means "Don't Care".
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