F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

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ID 750200
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile 25G Ethernet Single-Channel Design Example 3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration 4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives 5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Generating Tile Files 1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile 25G Ethernet Single-Channel Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing
3.3. Functional Description x
3.3.1. Design Components
3.4. Simulation x
3.4.1. Testbench 3.4.2. Simulation Design Example Components 3.4.3. Test Case—Single-Channel Design Example with Dynamic Reconfiguration
3.5. Hardware Testing x
3.5.1. Test Procedure
1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

1.2. Generating the Design Example

Figure 3. Procedure
Figure 4. Example Design Tab in theF-Tile 25G Ethernet Intel FPGA IP Parameter Editor

Follow these steps to generate the hardware design example and testbench:

  1. In the Intel® Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
  2. In the IP Catalog, locate and select F-Tile 25G Ethernet Intel FPGA IP . The New IP Variation window appears.
  3. Specify a top-level name for your IP variation and click OK. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
  4. In the Intel® Quartus® Prime Pro Edition software, you must select a specific Intel Agilex® 7 device in the Device field, or keep the default device the Intel® Quartus® Prime software proposes.
    Note: The hardware design example overwrites the selection with the device on the target board. You specify the target board from the menu of design example options in the Example Design tab.
  5. Click OK. The parameter editor appears.
  6. On the IP tab, specify the parameters for your IP core variation.
  7. On the Example Design tab, for Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware design example. Only Verilog HDL files are generated.
    Note: A functional VHDL IP core is not available. Specify Verilog HDL only, for your IP core design example.
  8. For Target Development Kit, select the Agilex I-series Transceiver-SoC Dev Kit
  9. Click the Generate Example Design button. The Select Example Design Directory window appears.
  10. If you wish to modify the design example directory path or name from the defaults displayed (alt_e25_f_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).
  11. Click OK.

Section Content
Design Example Parameters

Level Two Title