F-Tile 25G Ethernet Intel® FPGA IP User Guide

ID 750198
Date 4/15/2024
Public

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7.8. Clock Signals

The F-Tile Reference and System PLL Clocks Intel® FPGA IP is required to generate i_clk_ref and i_clk_sys input clocks that drive this IP core.

Table 21.  Clock Signals
Signal Name Direction Width Description
i_clk_ref Input 1

156.25 MHz transceiver reference clock. You must specify this frequency in the F-Tile Reference and System PLL Clock Intel® FPGA IP FGT refclk frequency IP parameter.

Connect this signal to the out_refclk_fgt_<i> output signal of the F-Tile Reference and System PLL Clocks Intel® FPGA IP.

i_clk_sys Input 1

805.6640625 MHz Ethernet system clock. You must specify this frequency in the F-Tile Reference and System PLL Clock Intel® FPGA IP Mode of system PLL IP parameter.

Connect this signal to the out_systempll_clk_<i> signal of the F-Tile Reference and System PLL Clocks Intel® FPGA IP.