AN 987: Static Update Partial Reconfiguration Tutorial: for Intel Agilex® 7 FPGA Development Board

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ID 749443
Date 1/16/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Static Update Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board
1. Static Update Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board x
1.1. Tutorial Requirements 1.2. Reference Design Overview 1.3. Static Update Region Overview 1.4. Download Reference Design Files 1.5. Reference Design Walkthrough 1.6. Document Revision History of AN 987: Static Update Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board
1.5. Reference Design Walkthrough x
1.5.1. Step 1: Getting Started 1.5.2. Step 2: Create Design Partitions 1.5.3. Step 3: Allocate Placement and Routing Regions 1.5.4. Step 4: Define Personas 1.5.5. Step 5: Create Revisions 1.5.6. Step 6: Compile the Base Revision 1.5.7. Step 7: Set Up PR Implementation Revisions 1.5.8. Step 8: Change the SUPR Logic 1.5.9. Step 9: Program the Board 1.5.10. Modifying the SUPR Partition
1.5.5. Step 5: Create Revisions x
1.5.5.1. Setting the Base Revision 1.5.5.2. Creating Implementation Revisions
1.5.9. Step 9: Program the Board x
1.5.9.1. Troubleshooting PR Programming Errors
Answers to Top FAQs
1. Static Update Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board

1.5.1. Step 1: Getting Started

To copy the reference design files to your working environment and compile the blinking_led flat design:
  1. Before you begin, Download Reference Design Files.
  2. Create the agilex7_pcie_devkit_blinking_led_supr directory in your working environment.
  3. Copy the appropriate downloaded subfolders for your target device to your working directory:
    • tutorials/agilex7f_pcie_devkit_blinking_led_supr/flat
    • tutorials/agilex7m_pcie_devkit_blinking_led_supr/flat
  4. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and open /flat/blinking_led.qpf.
  5. To compile the base design, click Processing > Start Compilation. The Timing Analyzer reports open automatically when compilation is complete. You can close the Timing Analyzer for now.
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