Nios® V Processor Software Developer Handbook

ID 743810
Date 7/08/2024
Public
Document Table of Contents

16.2.3.1. juart-terminal

Synopsis

juart-terminal [TERMINAL OPTIONS] [CONNECTION OPTIONS] [TARGET OPTIONS]

Description

Performs terminal I/O with a JTAG UART in a Nios® V processor-based system.

Usage

#connect to JTAG UART at cable 1
juart-terminal -c 1

Terminal Options

Terminal Options Description
V, --version Display version number
-h, --help Show this message and exit
-v, --verbose Show extra information during run (default)
-q, --quiet Show minimal information
--write-pid Write process ID to filename specified
-w, --wait Wait for a signal before starting
--signal-pid Send signal to process ID when ready
--flush Empty buffers before displaying output
-o, --quit-after=SECS Quit after SECS seconds. Default is never.
--no-quit-on-ctrl-d Do not quit if Ctrl-D received from target
-u, --dump=OPTS Dump extra debug information for OPTS

Connection Options

Connection Option Description
-H, --hardware Connect to a hardware target (default)
--persistent Try to reconnect after an I/O error
--no-persistent Opposite of persistent

Target Option

Target Option Description
-c, --cable=CABLE Use <CABLE JTAG> cable (default auto-detect)
-d, --device=DEVICE Connect to <DEVICE> device (default auto-detect)
-i, --instance=INSTANCE Connect to <INSTANCE> instance (default auto-detect)

Specifying Cable, Device, and Instance

1) AGF FPGA Development Kit on Intel® FPGA Download Cable [USB-0]
   (JTAG Server Version 22.1.0 Build 174 03/30/2022 SC Pro Edition)
  C341A0DD   AGFB014R24A(.|R1|R2)/.. (IR=10)
    Design hash 
    + Node 00486E00  Source/Probe #0
    + Node 08986E00  Nios V #0
    + Node 08986E01  Nios V #1
    + Node 0C006E00  JTAG UART #0
    + Node 0C006E01  JTAG UART #1
  031830DD   10M16S(A|C|L) (IR=10)
    Design hash
    + Node 08986E00  Nios V #0
    + Node 0C006E00  JTAG UART #0

2) Stratix 10H SoC Dev Kit on Intel® FPGA Download Cable [USB-1]
   (JTAG Server Version 22.1.0 Build 174 03/30/2022 SC Pro Edition)
  C322D0DD   1SX280HH1(.|S3)/1SX280HH2/.. (IR=10)
    Design hash 
    + Node 00486E00  Source/Probe #0
    + Node 08986E00  Nios V #0
    + Node 08986E01  Nios V #1
    + Node 0C006E00  JTAG UART #0
    + Node 0C006E01  JTAG UART #1
Table 56.  Selecting Target JTAG UART
Arguments Target JTAG UART
--cable=1 --device=1 --instance=0

Cable 1

1) AGF FPGA Development Kit on Intel® FPGA Download Cable [USB-0]

Device 1

C341A0DD AGFB014R24A

Instance 0

Node 0C006E00 JTAG UART #0

--cable=1 --device=2 --instance=0

Cable 1

1) AGF FPGA Development Kit on Intel® FPGA Download Cable [USB-0]

Device 2

031830DD 10M16S

Instance 0

Node 0C006E00 JTAG UART #0

--cable=2 --device=1 --instance=1

Cable 2

2) Stratix 10H SoC Dev Kit on Intel® FPGA Download Cable [USB-1]

Device 1

C322D0DD 1SX280HH1

Instance 1

Node 0C006E01 JTAG UART #1