Nios® V Processor Software Developer Handbook

ID 743810
Date 10/12/2024
Public
Document Table of Contents

10.4. Managing Cache in Multi-Master and Multi-Processor Systems

The Nios® V processor does not provide hardware cache coherency. Instead, software cache coherency must be provided when communicating through shared memory. The data cache contents of all processors accessing the shared memory must be managed by software to ensure that all masters read the most recent values and not overwrite new data with stale data. This management is done by using the data cache flushing and bypassing facilities to move data between the shared memory and the data cache(s) as needed.