Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

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ID 741330
Date 4/17/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA 3. Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide Archive 4. Document Revision History for the Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Hardware Limitations
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clock and Reset Signals
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure
1. Quick Start Guide
2. 10/100/1000 Multiport Ethernet MAC Design Example with 1000BASE-X/SGMII PCS and Embedded PMA
3. Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide Archive
4. Document Revision History for the Triple-Speed Ethernet Intel Agilex® 7 FPGA IP Design Example User Guide

2.4. Simulation

The simulation test case performs the following steps:
  1. Starts up the design example with an operating speed of 1G.
  2. Configures the Triple-Speed Ethernet MAC and PCS registers.
  3. Waits until the assertion of the measure valid signal.
  4. Sends non-PTP packets to port 0.
  5. MAC RX port 0 sends the received packets to MAC TX port 1.

When simulation ends, the values of the MAC statistics counters for port 3 are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters of port 3 are equal to the TX MAC statistics counters of port 0.


Section Content
Testbench

Level Two Title