F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 741328
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide 2. About F-Tile Triple-Speed Ethernet Intel® FPGA IP 3. Getting Started 4. Parameter Settings 5. Functional Description 6. Configuration Register Space 7. Interface Signals 8. Design Considerations 9. Timing Constraints 10. Software Programming Interface 11. F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 12. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide A. Ethernet Frame Format B. Simulation Parameters
2. About F-Tile Triple-Speed Ethernet Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Features 2.4. 10/100/1000 Ethernet MAC Versus Small MAC 2.5. High-Level Block Diagrams 2.6. Example Applications 2.7. IP Verification 2.8. Performance and Resource Utilization
2.7. IP Verification x
2.7.1. Optical Platform 2.7.2. Copper Platform
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Core Parameters and Options 3.4. IP Core Generation Output 3.5. Simulating Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IPs x
3.2.1. Intel® FPGA IP Evaluation Mode
3.4. IP Core Generation Output x
3.4.1. Design Constraint File
4. Parameter Settings x
4.1. Core Configuration 4.2. Ethernet MAC Options 4.3. FIFO Options 4.4. Timestamp Options 4.5. PCS/Transceiver Options
5. Functional Description x
5.1. 10/100/1000 Ethernet MAC 5.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA 5.3. Precision Time Protocol 5.4. Deterministic Latency
5.1. 10/100/1000 Ethernet MAC x
5.1.1. MAC Architecture 5.1.2. MAC Interfaces 5.1.3. MAC Transmit Datapath 5.1.4. MAC Receive Datapath 5.1.5. MAC Transmit and Receive Latencies 5.1.6. FIFO Buffer Thresholds 5.1.7. Congestion and Flow Control 5.1.8. Magic Packets 5.1.9. MAC Local Loopback 5.1.10. MAC Reset 5.1.11. PHY Management (MDIO) 5.1.12. Connecting MAC to External PHYs
5.1.3. MAC Transmit Datapath x
5.1.3.1. IP Payload Re-alignment 5.1.3.2. Address Insertion 5.1.3.3. Frame Payload Padding 5.1.3.4. CRC-32 Generation 5.1.3.5. Interpacket Gap Insertion 5.1.3.6. Collision Detection in Half-Duplex Mode
5.1.4. MAC Receive Datapath x
5.1.4.1. Preamble Processing 5.1.4.2. Collision Detection in Half-Duplex Mode 5.1.4.3. Address Checking 5.1.4.4. Frame Type Validation 5.1.4.5. Payload Pad Removal 5.1.4.6. CRC Checking 5.1.4.7. Length Checking 5.1.4.8. Frame Writing 5.1.4.9. IP Payload Alignment
5.1.4.3. Address Checking x
5.1.4.3.1. Unicast Address Checking 5.1.4.3.2. Multicast Address Resolution
5.1.6. FIFO Buffer Thresholds x
5.1.6.1. Receive Thresholds 5.1.6.2. Transmit Thresholds 5.1.6.3. Transmit FIFO Buffer Underflow
5.1.7. Congestion and Flow Control x
5.1.7.1. Remote Device Congestion 5.1.7.2. Receive FIFO Buffer and Local Device Congestion
5.1.8. Magic Packets x
5.1.8.1. Sleep Mode 5.1.8.2. Magic Packet Detection
5.1.11. PHY Management (MDIO) x
5.1.11.1. MDIO Connection 5.1.11.2. MDIO Frame Format
5.1.12. Connecting MAC to External PHYs x
5.1.12.1. Gigabit Ethernet 5.1.12.2. Programmable 10/100 Ethernet 5.1.12.3. Programmable 10/100/1000 Ethernet Operation
5.2. 1000BASE-X/SGMII PCS With Optional Embedded PMA x
5.2.1. 1000BASE-X/SGMII PCS Architecture 5.2.2. Transmit Operation 5.2.3. Receive Operation 5.2.4. Transmit and Receive Latencies 5.2.5. GMII Converter 5.2.6. SGMII Converter 5.2.7. Auto-Negotiation 5.2.8. Ten-bit Interface 5.2.9. 1000BASE-X/SGMII PCS Reset
5.2.2. Transmit Operation x
5.2.2.1. Frame Encapsulation 5.2.2.2. 8b/10b Encoding
5.2.3. Receive Operation x
5.2.3.1. Comma Detection 5.2.3.2. 8b/10b Decoding 5.2.3.3. Frame De-encapsulation 5.2.3.4. Synchronization 5.2.3.5. Carrier Sense 5.2.3.6. Collision Detection
5.2.6. SGMII Converter x
5.2.6.1. Transmit 5.2.6.2. Receive
5.2.7. Auto-Negotiation x
5.2.7.1. 1000BASE-X Auto-Negotiation 5.2.7.2. SGMII Auto-Negotiation
5.3. Precision Time Protocol x
5.3.1. IEEE 1588v2 Supported Configurations 5.3.2. IEEE 1588v2 Features 5.3.3. IEEE 1588v2 Architecture 5.3.4. IEEE 1588v2 Transmit Datapath 5.3.5. IEEE 1588v2 Receive Datapath 5.3.6. IEEE 1588v2 Frame Format
5.3.6. IEEE 1588v2 Frame Format x
5.3.6.1. PTP Frame in IEEE 802.3 5.3.6.2. PTP Frame over UDP/IPv4 5.3.6.3. PTP Frame over UDP/IPv6
6. Configuration Register Space x
6.1. MAC Configuration Register Space 6.2. PCS Configuration Register Space 6.3. Register Initialization
6.1. MAC Configuration Register Space x
6.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) 6.1.2. Statistics Counters (Dword Offset 0x18 – 0x38) 6.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B) 6.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7) 6.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6) 6.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3) 6.1.7. IEEE 1588v2 Feature PMA Delay
6.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17) x
6.1.1.1. Command_Config Register (Dword Offset 0x02)
6.2. PCS Configuration Register Space x
6.2.1. Control Register (Word Offset 0x00) 6.2.2. Status Register (Word Offset 0x01) 6.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) 6.2.4. An_Expansion Register (Word Offset 0x06) 6.2.5. If_Mode Register (Word Offset 0x14)
6.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05) x
6.2.3.1. 1000BASE-X 6.2.3.2. SGMII MAC Mode Auto Negotiation 6.2.3.3. SGMII PHY Mode Auto Negotiation
6.3. Register Initialization x
6.3.1. Triple-Speed Ethernet System with MII/GMII 6.3.2. Triple-Speed Ethernet System with SGMII 6.3.3. Triple-Speed Ethernet System with 1000BASE-X Interface
7. Interface Signals x
7.1. Interface Signals 7.2. Timing
7.1. Interface Signals x
7.1.1. 10/100/1000 Ethernet MAC Signals 7.1.2. 10/100/1000 Multiport Ethernet MAC Signals 7.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals 7.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile) 7.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals 7.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 , 1000BASE-X/SGMII 2XTBI PCS, and Embedded Serial PMA Signals 7.1.7. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals 7.1.8. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 7.1.9. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals 7.1.10. 1000BASE-X/SGMII PCS Signals 7.1.11. 1000BASE-X/SGMII 2XTBI PCS Signals 7.1.12. 1000BASE-X/SGMII PCS and PMA Signals
7.1.1. 10/100/1000 Ethernet MAC Signals x
7.1.1.1. Clock and Reset Signals 7.1.1.2. Clock Enabler Signals 7.1.1.3. MAC Control Interface Signals 7.1.1.4. MAC Status Signals 7.1.1.5. MAC Receive Interface Signals 7.1.1.6. MAC Transmit Interface Signals 7.1.1.7. Pause and Magic Packet Signals 7.1.1.8. MII/GMII/RGMII Signals 7.1.1.9. PHY Management Signals 7.1.1.10. ECC Status Signals
7.1.2. 10/100/1000 Multiport Ethernet MAC Signals x
7.1.2.1. Multiport MAC Clock and Reset Signals 7.1.2.2. Multiport MAC Receive Interface Signals 7.1.2.3. Multiport MAC Transmit Interface Signals 7.1.2.4. Multiport MAC Packet Classification Signals 7.1.2.5. Multiport MAC FIFO Status Signals
7.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals x
7.1.3.1. TBI Interface Signals 7.1.3.2. Status LED Control Signals 7.1.3.3. SERDES Control Signals 7.1.3.4. ECC Status Signals
7.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile) x
7.1.4.1. GMII Clock Signals 7.1.4.2. F-Tile Transceiver Direct PHY Signals
7.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 , 1000BASE-X/SGMII 2XTBI PCS, and Embedded Serial PMA Signals x
7.1.6.1. Deterministic Latency Clock Signals 7.1.6.2. IEEE 1588v2 RX Timestamp Signals 7.1.6.3. IEEE 1588v2 TX Timestamp Signals 7.1.6.4. IEEE 1588v2 TX Timestamp Request Signals 7.1.6.5. IEEE 1588v2 TX Insert Control Timestamp Signals 7.1.6.6. IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals 7.1.6.7. IEEE 1588v2 PCS Phase Measurement Clock Signal
7.1.8. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals x
7.1.8.1. 1.25 Gbps Serial Interface 7.1.8.2. Transceiver Native PHY Signal 7.1.8.3. Altera LVDS Transmitter and Receiver Soft-CDR I/O Signals
7.1.10. 1000BASE-X/SGMII PCS Signals x
7.1.10.1. PCS Control Interface Signals 7.1.10.2. PCS Reset Signals 7.1.10.3. MII/GMII Clocks and Clock Enablers 7.1.10.4. GMII 7.1.10.5. MII 7.1.10.6. SGMII Status Signals
7.1.11. 1000BASE-X/SGMII 2XTBI PCS Signals x
7.1.11.1. Clock Enablers 7.1.11.2. PCS Reset Signals 7.1.11.3. TBI Interface Signals
7.2. Timing x
7.2.1. Avalon Streaming Receive Interface 7.2.2. Avalon Streaming Transmit Interface 7.2.3. GMII Transmit 7.2.4. GMII Receive 7.2.5. RGMII Transmit 7.2.6. RGMII Receive 7.2.7. MII Transmit 7.2.8. MII Receive 7.2.9. IEEE 1588v2 Timestamp
8. Design Considerations x
8.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA 8.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O 8.3. Exposed Ports in the New User Interface 8.4. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA
8.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA x
8.1.1. MAC and PCS With LVDS Soft-CDR I/O
9. Timing Constraints x
9.1. Creating Clock Constraints 9.2. Recommended Clock Frequency
10. Software Programming Interface x
10.1. Driver Architecture 10.2. Directory Structure 10.3. PHY Definition 10.4. Using Multiple SG-DMA Descriptors 10.5. Using Jumbo Frames 10.6. API Functions 10.7. Constants
10.6. API Functions x
10.6.1. alt_tse_mac_get_common_speed() 10.6.2. alt_tse_mac_set_common_speed() 10.6.3. alt_tse_phy_add_profile() 10.6.4. alt_tse_system_add_sys() 10.6.5. triple_speed_ethernet_init() 10.6.6. tse_mac_close() 10.6.7. tse_mac_raw_send() 10.6.8. tse_mac_setGMII mode() 10.6.9. tse_mac_setMIImode() 10.6.10. tse_mac_SwReset()
A. Ethernet Frame Format x
A.1. Basic Frame Format A.2. VLAN and Stacked VLAN Frame Format A.3. Pause Frame Format
A.3. Pause Frame Format x
A.3.1. Pause Frame Generation
B. Simulation Parameters x
B.1. Functionality Configuration Parameters B.2. Test Configuration Parameters
1. About the F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide
2. About F-Tile Triple-Speed Ethernet Intel® FPGA IP
3. Getting Started
4. Parameter Settings
5. Functional Description
6. Configuration Register Space
7. Interface Signals
8. Design Considerations
9. Timing Constraints
10. Software Programming Interface
11. F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
12. Document Revision History for the F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide
A. Ethernet Frame Format
B. Simulation Parameters

9.1. Creating Clock Constraints

After you generate and integrate the IP into the system, you need to create a timing constraints file to specify the clock constraint requirement.

You can specify the clock requirement in the timing constraint file using the following command:

create_clock

For example, for a new clock named "reg_clk", with a 50 MHz clock targeted to the top level input port "clk", enter the following command line:

create_clock -name "reg_clk" -period "50 MHz" [get_ports "clk"]

Figure below shows an example of how you can create a timing constraint file to constrain the IP clocks.

Figure 81. Timing Constraint ExampleThe reconfig_clk signal is not shown in this example. Constrain the reconfig_clk based on your design implementation.


The example above consists of the following Verilog modules:

  • TOP.v—The top level design module which contains an Altera FPGA PLL and a user-defined instance. The top level input clocks consist of pll_inclk, ext_clk, and xcvr_ref_clk.
  • user_instance.v—The user-defined instance that instantiates the IP.
  • tse_variation.v—A Triple-Speed Ethernet Intel® FPGA IP variation. This example uses a 10/100/1000-Mbps Ethernet MAC with an internal FIFO buffer, a 1000BASE-X/SGMII PCS, and an embedded PMA.

The frequency for the PLL clock input, inclk0, is 100 MHz, and the frequency for the PLL clock output, c0, is 100 MHz. The Triple-Speed Ethernet MAC Avalon streaming clocks, ff_tx_clk and ff_rx_clk, use c0 as the clock source. The input clock frequency for the transceiver reference clock, xcvr_ref_clk, is 125 MHz.

Example of the IP timing constraint file: 

# PLL clock input, 100 MHz
create_clock -name pll_inclk -period 10.000 [get_ports {pll_inclk}]

# ext_clk, 50 MHz
create_clock -name ext_clk -period 20.000 [get_ports {ext_clk}]

# xcvr_ref_clk, 125 MHz
create_clock -name xcvr_ref_clk -period 8.000 [get_ports {xcvr_ref_clk}]

# Derive PLL generated output clocks.
derive_pll_clocks
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