HDMI PHY Intel FPGA IP Design Example User Guide

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ID 732781
Date 7/20/2022
Public
Document Table of Contents
Document Table of Contents x
1. HDMI PHY Design Example Quick Start Guide for Intel® Arria® 10 Devices 2. HDMI 2.0 PHY Design Example 3. Document Revision History for the HDMI PHY Intel FPGA IP Design Example User Guide
1. HDMI PHY Design Example Quick Start Guide for Intel® Arria® 10 Devices x
1.1. Generating the Design 1.2. Compiling and Testing the Design 1.3. HDMI PHY Intel® FPGA IP Design Example Parameters
2. HDMI 2.0 PHY Design Example x
2.1. Hardware and Software Requirements 2.2. Directory Structure 2.3. Reconfiguration Sequence Flow 2.4. Interface Signals 2.5. Clocking Scheme 2.6. Hardware Setup
2.1. Hardware and Software Requirements x
2.1.1. Hardware 2.1.2. Software
1. HDMI PHY Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.0 PHY Design Example
3. Document Revision History for the HDMI PHY Intel FPGA IP Design Example User Guide

2.3. Reconfiguration Sequence Flow

Figure 5. Multi-rate Reconfiguration Sequence FlowThe figure illustrates the multi-rate reconfiguration sequence flow of the controller when it receives input data stream and reference clock frequency, or when the transceiver is unlocked.
Figure 6. Reconfiguration Sequence FlowThe figure illustrates the Nios II software flow that involves the controls for I2C master and HDMI TX PHY.
Level Two Title