HDMI PHY Intel FPGA IP Design Example User Guide

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ID 732781
Date 7/20/2022
Public
Document Table of Contents
Document Table of Contents x
1. HDMI PHY Design Example Quick Start Guide for Intel® Arria® 10 Devices 2. HDMI 2.0 PHY Design Example 3. Document Revision History for the HDMI PHY Intel FPGA IP Design Example User Guide
1. HDMI PHY Design Example Quick Start Guide for Intel® Arria® 10 Devices x
1.1. Generating the Design 1.2. Compiling and Testing the Design 1.3. HDMI PHY Intel® FPGA IP Design Example Parameters
2. HDMI 2.0 PHY Design Example x
2.1. Hardware and Software Requirements 2.2. Directory Structure 2.3. Reconfiguration Sequence Flow 2.4. Interface Signals 2.5. Clocking Scheme 2.6. Hardware Setup
2.1. Hardware and Software Requirements x
2.1.1. Hardware 2.1.2. Software
1. HDMI PHY Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.0 PHY Design Example
3. Document Revision History for the HDMI PHY Intel FPGA IP Design Example User Guide

2.4. Interface Signals

The tables list the signals for the HDMI PHY Intel® FPGA IP design example.
Table 3.  Top-Level Signals
Signal Direction Width Description
On-board Oscillator Signal
clk_fpga_b3_p

Input

 1

100 MHz free running clock for core reference clock
refclk_fmcb_p Input 1

Fixed rate reference clock for power-up calibration of the transceiver. It is 625 MHz by default but can be of any frequency
User Push Buttons and LEDs
cpu_resetn

Input

 1

Global reset
user_led_g

Output

 2

Green LED display
HDMI FMC Daughter Card Pins on FMC Port B
fmcb_gbtclk_m2c_p_0

Input

1

 HDMI RX TMDS clock
fmcb_dp_m2c_p

Input

 3

HDMI RX red, green, and blue data channels

  • Bitec daughter card revision 11
    • [0]: RX TMDS Channel 1 (Green)
    • [1]: RX TMDS Channel 2 (Red)
    • [2]: RX TMDS Channel 0 (Blue)
fmcb_dp_c2m_p

Output

 4

HDMI TX clock, red, green, and blue data channels

  • Bitec daughter card revision 11
    • [0]: TX TMDS Channel 2 (Red)
    • [1]: TX TMDS Channel 1 (Green)
    • [2]: TX TMDS Channel 0 (Blue)
    • [3]: TX TMDS Clock Channel
fmcb_la_rx_p_9

Input

 1

HDMI RX +5V power detect

fmcb_la_rx_p_8

Input

 1 HDMI RX hot plug detect
fmcb_la_rx_n_8

Input

 1

HDMI RX I2C SDA for DDC and SCDC

fmcb_la_tx_p_10

Input

 1 HDMI RX I2C SCL for DDC and SCDC
fmcb_la_tx_p_12

Input

 1 HDMI TX hot plug detect
fmcb_la_tx_n_12

Input

 1 HDMI I2C SDA for DDC and SCDC
fmcb_la_rx_p_10

Input

 1

HDMI I2C SCL for DDC and SCDC

fmcb_la_tx_p_11

Input

 1 HDMI I2C SDA for redriver control
fmcb_la_rx_n_9

Input

 1

HDMI I2C SCL for redriver control

Level Two Title