HDMI PHY Intel FPGA IP User Guide

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ID 732147
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. HDMI PHY Intel® FPGA IP Quick Reference 2. HDMI PHY Overview 3. HDMI PHY Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI RX PHY 6. HDMI TX PHY 7. PHY Arbiter and Transceiver Merging 8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide
2. HDMI PHY Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI PHY Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel® Arria® 10 4.2. HDMI Hardware Design Examples for Intel® Agilex™ F-Tile
5. HDMI RX PHY x
5.1. HDMI 2.0 (Support FRL = 0) 5.2. HDMI 2.1 (Support FRL = 1)
5.1. HDMI 2.0 (Support FRL = 0) x
5.1.1. Architecture 5.1.2. Dynamic Reconfiguration 5.1.3. IP Ports 5.1.4. IP Configuration Parameters 5.1.5. RX PHY Address Map
5.2. HDMI 2.1 (Support FRL = 1) x
5.2.1. Architecture 5.2.2. Dynamic Reconfiguration 5.2.3. IP Ports 5.2.4. IP Configuration Parameters 5.2.5. RX PHY Address Map
6. HDMI TX PHY x
6.1. HDMI 2.0 (Support FRL = 0) 6.2. HDMI 2.1 (Support FRL = 1)
6.1. HDMI 2.0 (Support FRL = 0) x
6.1.1. Architecture 6.1.2. Dynamic Reconfiguration 6.1.3. IP Ports 6.1.4. IP Configuration Parameters 6.1.5. TX PHY Address Map
6.2. HDMI 2.1 (Support FRL = 1) x
6.2.1. Architecture 6.2.2. Dynamic Reconfiguration 6.2.3. IP Ports 6.2.4. IP Configuration Parameters 6.2.5. TX PHY Address Map
7. PHY Arbiter and Transceiver Merging x
7.1. PHY Arbiter IP Ports 7.2. IP Configuration Parameters 7.3. PHY Merging and Arbiter Connection
7.3. PHY Merging and Arbiter Connection x
7.3.1. RX-Only and TX-Only Use Cases 7.3.2. Single RX and TX Simple Merge 7.3.3. Complex Straddled Channels
1. HDMI PHY Intel® FPGA IP Quick Reference
2. HDMI PHY Overview
3. HDMI PHY Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI RX PHY
6. HDMI TX PHY
7. PHY Arbiter and Transceiver Merging
8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide

5.1.3. IP Ports

Table 10.  HDMI RX PHY Intel FPGA IP Ports
Interface Port Type Clock Domain Port Direction Description
mgmt_clk Clock — mgmt_clk Input Free-running system clock input (100 MHz).
fr_clk Clock — fr_clk Input Free-running clock for the transceiver power-up calibration. This clock can be at any frequency value in the range 61-800 MHz (Intel recommends 100 MHz).
rx_tmds_clk Clock — rx_tmds_clk Input This clock frequency follows the TMDS clock frequency.
rx_serial_data Conduit rx_tmds_clk rx_serial_data [2:0] Input HDMI serial RX data stream.
reset Reset reset Input Main asynchronous reset.
irq Interrupt mgmt_clk irq Output Interrupt signal - reserved for future use (not currently supported).
phy_interface Conduit — rx_clk [2:0] Output RX recovered clocks.
— vid_clk Output Synchronous video clock.
— ls_clk Output Link speed clock.
rx_clk rx_parallel_data [59:0] Output RX parallel data. 20 Bits per associated rx_clk(i.e., rx_parallel_data [19:0] with rx_clk[0], 39:20 with rx_clk[1], etc).
mgmt_clk in_lock Output Indicates all transceivers are locked.
mgmt_clk tmds_bit_clock_ratio Input ‘0’ => rx_tmds_clk = 1/10 serial data rate; ‘1’ => rx_tmds_clk = 1/40 serial data rate.
ls_clk locked Input Indicates the connected HDMI RX Intel FPGA IP has achieved video lock.
mgmt_clk os Output ‘0’ = > rx_parallel_data is not oversampled. ‘1’ => oversampling ratio of 5.
mgmt_clk i2c_trans_detected Input Indicates an I2C access has been detected by the HDMI RX Intel FPGA IP.
mgmt_clk i2c_trans_detected_ack Output Acknowledgement back to the HDMI RX Intel FPGA IP for the i2c_trans_detected signal to be cleared.
mgmt_clk color_depth [3:0] Input

0b0000 => color depth not indicated.

0b0100 => 8 bit color

0b0101 => 10 bit color

0b0110 => 12 bit color

0b0111 => 16 bit color

others => reserved.
av_mm_control Avalon memory-mapped mgmt_clk av_mm_control_write Input Avalon® memory-mapped interface for control of the IP core.
mgmt_clk av_mm_control_read Input
mgmt_clk av_mm_control_address Input
mgmt_clk av_mm_control_writedata Input
mgmt_clk av_mm_control_readdata Output
mgmt_clk av_mm_control_waitrequest Output
rxphy_rcfg_master Avalon memory-mapped mgmt_clk rxphy_rcfg_master_write Output Avalon® memory-mapped interface for reconfiguration of the transceivers – connects to the PHY arbiter.
mgmt_clk rxphy_rcfg_master_read Output Only valid when SEPARATE_RCFG_INTF_EN = 0.
mgmt_clk rxphy_rcfg_master_address [9:0] Output
mgmt_clk rxphy_rcfg_master_writedata [31:0] Output
mgmt_clk rxphy_rcfg_master_readdata [31:0] Input
mgmt_clk rxphy_rcfg_master_waitrequest Input
rxphy_rcfg_slave Conduit mgmt_clk rxphy_rcfg_slave_write [3:0] Input

4x Avalon® memory-mapped interface with extra signals for reconfiguration of the transceivers – connects to the PHY arbiter.

rxphy_reconfig_en signals to PHY arbiter that RX PHY requires access to transceivers.

rxphy_cal_busy signals from each transceiver that calibration is in progress.

rxphy_reconfig_cal_busy signals back from the PHY arbiter that transceiver is undergoing calibration or reconfiguration.

rxphy_rcfg_slave_chan indicates which transceiver is to be accessed. Only valid when SEPARATE_RCFG_INTF_EN = 0.

mgmt_clk rxphy_rcfg_slave_read [3:0] Input
mgmt_clk rxphy_rcfg_slave_address [39:0] Input
mgmt_clk rxphy_rcfg_slave_writedata [127:0] Input
mgmt_clk rxphy_rcfg_slave_readdata [127:0] Output
mgmt_clk rxphy_rcfg_slave_waitrequest [3:0] Output
mgmt_clk rxphy_reconfig_en Output
mgmt_clk rxphy_cal_busy [3:0] Input
mgmt_clk rxphy_reconfig_cal_busy [3:0] Output
mgmt_clk rxphy_rcfg_slave_chan [1:0] Output
rxphy_rcfg_master_# Avalon memory-mapped mgmt_clk rxphy_rcfg_master_write_# Output Avalon® memory-mapped interface for reconfiguration of transceivers – connects to PHY arbiter, one for each channel (indicated by #). Only valid when SEPARATE_RCFG_INTF_EN = 1.
mgmt_clk rxphy_rcfg_master_read_# Output
mgmt_clk rxphy_rcfg_master_address_# [9:0] Output
mgmt_clk rxphy_rcfg_master_writedata_# [31:0] Output
mgmt_clk rxphy_rcfg_master_readdata_# [31:0] Input
mgmt_clk rxphy_rcfg_master_waitrequest_# Input
rxphy_rcfg_slave_#(# values 2:0) Conduit mgmt_clk rxphy_rcfg_slave_write_# Input

Avalon® memory-mapped interface with extra signals for reconfiguration of transceivers – connects to PHY Arbiter, one for each transceiver channel.

rxphy_reconfig_en_# signals to PHY arbiter that RX PHY requires access to transceivers.

rxphy_cal_busy_# signals from each transceiver that calibration is in progress.

rxphy_reconfig_cal_busy_# signals back from PHY arbiter that transceiver is undergoing calibration or reconfiguration. Only valid when SEPARATE_RCFG_INTF_EN = 1.

mgmt_clk rxphy_rcfg_slave_read_# Input
mgmt_clk rxphy_rcfg_slave_address_# [9:0] Input
mgmt_clk rxphy_rcfg_slave_writedata_# [31:0]  
mgmt_clk rxphy_rcfg_slave_readdata_# [31:0] Output
mgmt_clk rxphy_rcfg_slave_waitrequest_# Output
  rxphy_reconfig_en_# Output
  rxphy_cal_busy_# Output
  rxphy_reconfig_cal_busy_# Input
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