HDMI PHY Intel FPGA IP User Guide

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ID 732147
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. HDMI PHY Intel® FPGA IP Quick Reference 2. HDMI PHY Overview 3. HDMI PHY Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI RX PHY 6. HDMI TX PHY 7. PHY Arbiter and Transceiver Merging 8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide
2. HDMI PHY Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI PHY Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel® Arria® 10 4.2. HDMI Hardware Design Examples for Intel® Agilex™ F-Tile
5. HDMI RX PHY x
5.1. HDMI 2.0 (Support FRL = 0) 5.2. HDMI 2.1 (Support FRL = 1)
5.1. HDMI 2.0 (Support FRL = 0) x
5.1.1. Architecture 5.1.2. Dynamic Reconfiguration 5.1.3. IP Ports 5.1.4. IP Configuration Parameters 5.1.5. RX PHY Address Map
5.2. HDMI 2.1 (Support FRL = 1) x
5.2.1. Architecture 5.2.2. Dynamic Reconfiguration 5.2.3. IP Ports 5.2.4. IP Configuration Parameters 5.2.5. RX PHY Address Map
6. HDMI TX PHY x
6.1. HDMI 2.0 (Support FRL = 0) 6.2. HDMI 2.1 (Support FRL = 1)
6.1. HDMI 2.0 (Support FRL = 0) x
6.1.1. Architecture 6.1.2. Dynamic Reconfiguration 6.1.3. IP Ports 6.1.4. IP Configuration Parameters 6.1.5. TX PHY Address Map
6.2. HDMI 2.1 (Support FRL = 1) x
6.2.1. Architecture 6.2.2. Dynamic Reconfiguration 6.2.3. IP Ports 6.2.4. IP Configuration Parameters 6.2.5. TX PHY Address Map
7. PHY Arbiter and Transceiver Merging x
7.1. PHY Arbiter IP Ports 7.2. IP Configuration Parameters 7.3. PHY Merging and Arbiter Connection
7.3. PHY Merging and Arbiter Connection x
7.3.1. RX-Only and TX-Only Use Cases 7.3.2. Single RX and TX Simple Merge 7.3.3. Complex Straddled Channels
1. HDMI PHY Intel® FPGA IP Quick Reference
2. HDMI PHY Overview
3. HDMI PHY Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI RX PHY
6. HDMI TX PHY
7. PHY Arbiter and Transceiver Merging
8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide

5.2.3. IP Ports

Table 22.  HDMI RX PHY Intel FPGA IP Ports
Interface Port Type Clock Domain Port Direction Description
reset Reset — reset Input Main asynchronous reset
mgmt_clk Clock — mgmt_clk Input Free-running system clock input (100 MHz)
rx_tmds_clk Clock — rx_tmds_clk Input This clock frequency follows TMDS clock frequency. This clock is connected to the TMDS clock input from the HDMI sink connector
i2c_clk Clock — i2c_clk Input Clock input for i2c (100 MHz)
systempll_clk Clock — systempll_clk Input

Reference clock to RX Transceiver System PLL Clock (100 MHz). This clock is driven by F-tile Reference and System PLL clock IP output

rx_phy_cdr_refclk_frl Clock — rx_phy_cdr_refclk_frl Input

Reference clock to RX Transceiver for FRL (100 MHz). This clock is driven by F-tile Reference and System PLL clock IP output
rx_phy_cdr_refclk_tmds Clock — rx_phy_cdr_refclk_tmds Input

Reference clock to RX Transceiver for TMDS. This clock is driven by F-tile Reference and System PLL clock IP output. Frequency depends on TMDS Clock frequency

rxphy_rcfg_master Avalon memory-mapped mgmt_clk rxphy_rcfg_master_write Output Avalon memory-mapped interface for reconfiguration of transceivers – connects to PHY Arbiter
rxphy_rcfg_master_read Output
rxphy_rcfg_master_address[9:0] Output
rxphy_rcfg_master_writedata[31:0] Output
rxphy_rcfg_master_readdata[31:0] Input
rxphy_rcfg_master_readdatavalid Input
rxphy_rcfg_master_waitrequest Input
av_mm_control Avalon memory-mapped mgmt_clk av_mm_control_write Input Avalon memory-mapped interface for control of IP core.
mgmt_clk av_mm_control_read Input
mgmt_clk av_mm_control_address [7:0] Input
mgmt_clk av_mm_control_writedata [31:0] Input
mgmt_clk av_mm_control_readdata [31:0] Output
rx_serial_data Conduit rx_phy_clk rx_serial_data[3:0] Input HDMI serial RX data stream
rx_serial_data_n Conduit rx_phy_clk rx_serial_data_n[3:0] Input HDMI serial RX data stream (negative polarity)
phy_interface Conduit — rx_frl_clk Output Clock to FRL path on the RX core. Refer to Section 5.5 FRL Clocking Scheme of HDMI Intel FPGA IP Core User Guide for more details
— rx_phy_clk [3:0] Output Clock out recovered from RX transceiver
rx_phy_clk rx_parallel_data[159:0] Output RX parallel data. 40 Bits per associated rx_phy_clk (i.e.rx_parallel_data[39:0] with rx_phy_clk[0], rx_parallel_data [79:40] with rx_phy_clk[1], etc)
mgmt_clk rx_os Output ‘0’ =>rx_parallel_data is not oversampled.

‘1’ => oversampling ratio of 5
— hdmi_5v_detect_n Input HDMI RX 5V detect and hotplug detect. Refer to the Sink Interfaces section in the HDMI Intel FPGA IP User Guide for more information
— rx_5v_detect Output
— device_ready Input Reset release IP signal indicates readiness of device upon power up
mgmt_clk sys_init Output Indicates readiness of reconfiguration management
mgmt_clk rx_tmds_freq [23:0] Output TMDS Frequency calculated by reconfiguration management block
mgmt_clk rx_tmds_freq_valid Output
mgmt_clk rx_phy_ready Output Indicates readiness of transceivers
mgmt_clk rx_core_in_lock Output Indicates all transceivers locked
mgmt_clk rxphy_rcfg_master_new_cfg_applied_ack Output Reconfiguration control registers
mgmt_clk rxphy_rcfg_busy Output
mgmt_clk rxphy_rcfg_curr_profile_id [14:0] Input
mgmt_clk rxphy_rcfg_master_new_cfg_applied Input
mgmt_clk rxphy_cal_busy_gated [3:0] Input
mgmt_clk rx_pll_tmds_locked Output Not used. To be cleaned up in a future release
mgmt_clk rx_pll_frl_locked Output Indicate FRL IOPLL is locked
mgmt_clk rx_core_locked Input Indicates connected HDMI RX Intel FPGA IP has achieved alignment lock
mgmt_clk pll_vid_clk_locked Input Indicates Video Clock IOPLL is locked
mgmt_clk rx_core_frl_locked [3:0] Input Indicates connected HDMI RX Intel FPGA IP has achieved FRL lock
mgmt_clk rx_core_frl_rate [3:0] Input

0 = TMDS

1 = 3000Mbps (3 lane)

2 = 6000Mbps (3 lane)

3 = 6000Mbps (4 lane)

4 = 8000Mbps (4 lane)

5 = 10000Mbps (4 lane)

6 = 12000Mbps (4 lane)

mgmt_clk rx_core_tmds_bit_clock_ratio Input

‘0’=> rx_tmds_clk = 1/10 serial data rate;

‘1’ => rx_tmds_clk = 1/40 serial data rate

Level Two Title