HDMI PHY Intel FPGA IP User Guide

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ID 732147
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. HDMI PHY Intel® FPGA IP Quick Reference 2. HDMI PHY Overview 3. HDMI PHY Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI RX PHY 6. HDMI TX PHY 7. PHY Arbiter and Transceiver Merging 8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide
2. HDMI PHY Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI PHY Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel® Arria® 10 4.2. HDMI Hardware Design Examples for Intel® Agilex™ F-Tile
5. HDMI RX PHY x
5.1. HDMI 2.0 (Support FRL = 0) 5.2. HDMI 2.1 (Support FRL = 1)
5.1. HDMI 2.0 (Support FRL = 0) x
5.1.1. Architecture 5.1.2. Dynamic Reconfiguration 5.1.3. IP Ports 5.1.4. IP Configuration Parameters 5.1.5. RX PHY Address Map
5.2. HDMI 2.1 (Support FRL = 1) x
5.2.1. Architecture 5.2.2. Dynamic Reconfiguration 5.2.3. IP Ports 5.2.4. IP Configuration Parameters 5.2.5. RX PHY Address Map
6. HDMI TX PHY x
6.1. HDMI 2.0 (Support FRL = 0) 6.2. HDMI 2.1 (Support FRL = 1)
6.1. HDMI 2.0 (Support FRL = 0) x
6.1.1. Architecture 6.1.2. Dynamic Reconfiguration 6.1.3. IP Ports 6.1.4. IP Configuration Parameters 6.1.5. TX PHY Address Map
6.2. HDMI 2.1 (Support FRL = 1) x
6.2.1. Architecture 6.2.2. Dynamic Reconfiguration 6.2.3. IP Ports 6.2.4. IP Configuration Parameters 6.2.5. TX PHY Address Map
7. PHY Arbiter and Transceiver Merging x
7.1. PHY Arbiter IP Ports 7.2. IP Configuration Parameters 7.3. PHY Merging and Arbiter Connection
7.3. PHY Merging and Arbiter Connection x
7.3.1. RX-Only and TX-Only Use Cases 7.3.2. Single RX and TX Simple Merge 7.3.3. Complex Straddled Channels
1. HDMI PHY Intel® FPGA IP Quick Reference
2. HDMI PHY Overview
3. HDMI PHY Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI RX PHY
6. HDMI TX PHY
7. PHY Arbiter and Transceiver Merging
8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide

5.1.4. IP Configuration Parameters

Layout options allow the transceiver polarity to be swapped and also the transceiver channel number to be matched to the HDMI data channel. This allows for flexibility in the PCB layout.

Separate reconfiguration interfaces are enabled when the transceiver merging requires the complex straddling of channels. Refer to the Complex Straddled Channels section for more information.

Table 11.  RX PHY Configuration Parameters
Parameter Value Description
Device family Arria 10 Targeted device family. This parameter inherits the value from the project device.
Supported HDMI Version 2.0 Currently only HDMI version 2.0 is supported.
Symbols per clock 2 symbols per clock Determines how many symbols are processed per clock.
Transceiver for Blue / TMDS 0 0, 1, 2 Selects which transceiver channel carries the blue / TMDS 0 data. This allows any lane swaps on the circuit board to be corrected.
Transceiver for Green / TMDS 1 0, 1, 2 Selects which transceiver channel carries the green / TMDS 1 data. This allows any lane swaps on the circuit board to be corrected.
Transceiver for Red / TMDS 2 0, 1, 2 Selects which transceiver channel carries the red / TMDS 2 data. This allows any lane swaps on the circuit board to be corrected.
Invert Transceiver 0 On, Off Inverts the data on transceiver 0. This can be used to correct for swapping the polarities round of the corresponding differential pair on the circuit board.
Invert Transceiver 1 On, Off Inverts the data on transceiver 1. This can be used to correct for swapping the polarities round of the corresponding differential pair on the circuit board.
Invert Transceiver 2 On, Off Inverts the data on transceiver 2. This can be used to correct for swapping the polarities round of the corresponding differential pair on the circuit board.
Enable Separate Configuration Interfaces On, Off This splits each combined rxphy_rcfg_master and rxphy_rcfg_slave conduit into three separate conduits, one for each transceiver channel. The purpose of this is to allow complex transceiver merging as described in section [missing section].
Enable Advanced Features On, Off This parameter is not supported.
Figure 5. RX PHY Configuration Parameters
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