HDMI PHY Intel FPGA IP User Guide

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ID 732147
Date 7/20/2022
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Document Table of Contents
Document Table of Contents x
1. HDMI PHY Intel® FPGA IP Quick Reference 2. HDMI PHY Overview 3. HDMI PHY Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI RX PHY 6. HDMI TX PHY 7. PHY Arbiter and Transceiver Merging 8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide
2. HDMI PHY Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI PHY Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel® Arria® 10
5. HDMI RX PHY x
5.1. Architecture 5.2. Dynamic Reconfiguration 5.3. IP Ports 5.4. IP Configuration Parameters 5.5. RX PHY Address Map
6. HDMI TX PHY x
6.1. Architecture 6.2. Dynamic Reconfiguration 6.3. IP Ports 6.4. IP Configuration Parameters 6.5. TX PHY Address Map
7. PHY Arbiter and Transceiver Merging x
7.1. PHY Arbiter IP Ports 7.2. IP Configuration Parameters 7.3. PHY Merging and Arbiter Connection
7.3. PHY Merging and Arbiter Connection x
7.3.1. RX Only and TX Only Use Cases 7.3.2. Single RX and TX Simple Merge 7.3.3. Complex Straddled Channels
1. HDMI PHY Intel® FPGA IP Quick Reference
2. HDMI PHY Overview
3. HDMI PHY Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI RX PHY
6. HDMI TX PHY
7. PHY Arbiter and Transceiver Merging
8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide

7.3.1. RX Only and TX Only Use Cases

In the TX only and RX only use cases, the unused configuration buses can be removed from the PHY Arbiter by unticking the appropriate Enable in the PHY Arbiter configuration parameters. This is shown in the following figures.

You must note that RX only means that only the RX part of the particular transceiver is used and the TX is unused (vice versa for TX only) – i.e. a design could have an RX PHY and Arbiter in RX only on one group of transceivers as well as a TX PHY and another Arbiter in TX only on a different group of transceivers.

Figure 9. RX Only PHY and Arbiter Configuration and Connection
Figure 10. TX Only PHY and Arbiter Configuration and Connection

The XCVR_RECONFIG_GROUP .qsf assignments are not necessary in this use case.

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