Visible to Intel only — GUID: ddo1713322839395
Ixiasoft
1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
Visible to Intel only — GUID: ddo1713322839395
Ixiasoft
6.1.1. Pilot System with Non-pipelined Nios V/m Processor
Altera recommends to use the non-pipelined Nios® V/m processor to allow full debugging capabilities. The architecture performance of a non-pipelined Nios® V/m processor is similar to the Nios® V/c processor, at the expense of bigger logic size.
Feature | Nios® V/c Processor | Non-pipelined Nios® V/m Processor |
---|---|---|
Debug Module | — | Supported |
Processor CSR | — | Supported |
Interrupt and Exceptions | — | Supported |
Logic Size (ALM) 10 | x1 | x1.5 |
DMIPS/Mhz Performance10 | x1 | x1 |
CoreMark/MHz Performance10 | x1 | x1 |
Internal Timer | — | Supported |
You can utilize Nios® V/m processor to debug Nios® V/c processor:
- Start the processor system using non-pipelined Nios® V/m processor.
- Turn on Enable Debug
- Turn off Enable Pipelining in CPU
- Ensure there is no interrupt or exception in the Nios® V/m processor system. Do not connect to the Interrupt Receiver on the processor.
Note: To implement a JTAG UART Intel® FPGA IP without interrupt, you can enable the small JTAG UART driver in the BSP Editor to apply polled operation. Ensure that the compile definition (ALTERA_AVALON_JTAG_UART_SMALL) is found in the toolchain.cmake.Figure 103. Nios® V/m Processor System with No InterruptFigure 104. Enable Small JTAG UART Driver in BSP Editor
- Develop the Nios® V processor software application in baremetal ( Intel® HAL).
- Program the design SOF file onto the Intel® FPGA device.
- Download the application ELF file into the Nios® V processor system.
- Perform design verification and debugging with the Nios® V/m processor core.
- Verify that the Nios® V/m processor is working successfully, then replace the Nios® V/m processor with Nios® V/c processor.
- Right-click the Nios® V/m processor, click Replace > Nios V/c Processor Intel FPGA IP.
- Reconfigure the same assignment in the IP Parameter Editor.
- Address any possible errors.
- Click Sync System Infos.
Figure 105. Nios® V/c Processor Replacement - Implement booting Nios® V/c processor from On-Chip Memory.
- Recreate the application BSP, APP, and ELF.
- Program the memory-initialized design SOF file onto the Intel® FPGA device.
- Power cycle the Intel® FPGA device.
Related Information
10 Relative to the Nios® V/c processor.