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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Embedded Processor Design Handbook Archives
9. Document Revision History for the Nios® V Embedded Processor Design Handbook
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios V Processor Booting from On-Chip Memory (OCRAM)
4.7. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.4.1. Prerequisites
6.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.4.3. Creating Nios V Processor Software
6.4.4. Generating Memory Initialization File
6.4.5. Generating System Simulation Files
6.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
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1.3.2.1.1. Generating the Nios® V/m Processor Example Design in Platform Designer
To generate the Nios® V/m processor example design in Platform Designer, perform the following steps:
- In the Intel® Quartus® Prime software, go to Tools ➤Platform Designer.
- In the Platform Designer, select IP Variant.
- For Quartus project, select None.
- In the IP Variant dialog box, specify any name for your IP.
Note: You do not need to save the IP later.
- Click Select in the Component type.
- The IP Catalog opens.
- Search for Nios V/m Processor Intel FPGA IP.
- Create the IP design.
- Click Example Design : "Hello World Example Design" and select your project folder. The .zip file is copied after you select the project folder.
Figure 2. IP Parameter Editor for Nios® V/m Processor Intel® FPGA IP
- Close the IP Parameter Editor. When prompted with Save changes?. Click Don’t Save.
- Unzip the example design to your project folder. Refer to the following table for the example design files and the description.
File | Description |
---|---|
software/app | Folder containing source code for software application. |
create_qsys.tcl | TCL script to generate the example design .qsys file. |
readme.txt | Description and steps to build the example design. |
toggle_issp.tcl | TCL script to reset the design via In-System Sources and Probes (ISSP). |
top.qpf | Example design Quartus Project File (.qpf) file. |
top.qsf | Example design Quartus Setting File (.qsf) file. |
top.sdc | Example design Synopsys* Design Constraints (.sdc) file. |
top.v | Top-level Verilog design. |