F-Tile SDI II Intel® FPGA IP Design Example User Guide

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ID 710496
Date 4/09/2024
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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile SDI II Intel® FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
1.5. Design Example Parameters x
1.5.1. Design Example Presets
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
2.5. Hardware Testing x
2.5.1. Parallel loopback 2.5.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile SDI II Intel® FPGA IP Design Example User Guide

4. Document Revision History for the F-Tile SDI II Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.04.09 24.1 19.5.0
  • Updated all mentions of Nios® II to Nios® V.
  • Updated the design example parameters to include Agilex™ I-Series SoC Development Kit FA and FB.
  • Updated the hardware requirements to include Agilex™ I-Series SoC Development Kit FA and FB.
2023.10.05 23.3 19.4.0
  • Fixed issues related to lock-to-reference clock and SD-standard high jitter.
  • Replaced Device Initialization module with System Reset module at design top level.
  • Updated the Components Required for TX- or RX-only Design on Agilex™ 7 Devices figure with System Reset and SDI RX PHY Access (1).
2023.09.15 23.1 19.3.2 Updated dip switch position in the Compiling and Testing the Design in Hardware topic.
2023.04.10 23.1 19.3.2
  • Updated the Select Board and Change Target Device descriptions in the Design Example Parameters chapter.
  • Corrected software requirement information.
  • Updated the RX Top/ TX Top/ Du Top Parameters table in the Interface Signal topic.
  • Updated product family name to "Intel Agilex 7".
2022.12.22 22.4 19.3.1 Added the Supported Video Formats for Design Examples with AXIS-VVP Full Enabled table to the Hardware Testing chapter.
2022.12.9 22.4 19.3.1 Added four design example presets to the Parameter Editor.
2022.10.21 22.3 19.3.0
  • Updated Directory Structure topic:
    • Updated Directory Structure for the Design Example figure.
    • Updated Other Generated Files in RTL Folder table.
  • Updated description for Select Design parameter in the Parameters available in the Design Example tab table in the Design Example Parameters topic.
  • Updated footnotes in all figures in the Functional Description topic.
  • Updated description for Device Under Test (DUT) Components table in the Design Components topic.
  • Updated description for Reference and System PLL Clocks parameter in the Common Blocks at Top Level table in the Design Components topic.
  • Updated footnotes in the following figures in the Clocking Schemes topic:
    • Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = None)
    • Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = None)
    • Serial Loopback with Simplex Mode
    • Serial Loopback with Duplex Mode
  • Updated description for TX PLL refclock in the Clocking Scheme Component table in the Clocking Scheme Component topic.
  • Updated footnotes in the following figures in the Testbench Components topic:
    • Simplex Mode Simulation Testbench Block Diagram
    • Duplex Mode Simulation Testbench Block Diagram
  • Updated description for clk_a_12c_fgt_p_4 signal in the Top Level Signals table in the Interface Signal topic.
2022.07.05 22.2 19.3.0
  • Added additional details under software in Hardware and Software Requirements section.
  • Added additional description for SDI II in Device Under Test (DUT) Components table.
  • Added footnote after Device Under Test (DUT) Components table.
  • Added additional description in Loopback Top Components table.
  • The following updates are made in the Functional Description section:
    • Updated figure title for Parallel Loopback with Simplex Mode to Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = None).
    • Added Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full) figure.
    • Updated figure title for Parallel Loopback with Duplex Mode to Parallel Loopback with Duplex Mode IP Core Enable active video data protocols = None).
    • Added Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full) figure.
    • Updated figure title for Serial Loopback with Simplex Mode to Serial Loopback with Simplex Mode IP Core [Agilex] (Enable active video data protocols = None).
    • Updated figure title for Serial Loopback with Duplex Mode to Serial loopback with duplex mode IP core (Enable active video data protocols = None).
    • Added note for Serial Loopback with Duplex Mode IP Core (Enable active video data protocols = None).
  • The following updates are made in the Clocking Scheme section:
    • Updated figure title for Parallel Loopback with Simplex Mode to Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = None).
    • Added Parallel Loopback with Simplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full) figure.
    • Updated figure title for Parallel Loopback with Duplex Mode to Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = None).
    • Added Parallel Loopback with Duplex Mode IP Core (Enable active video data protocols = AXIS-VVP Full) figure.
  • Added Diagram Label and Description details for AXIS clcok in Clocking Scheme Component table.
  • Added additional description for Enable active video data protocols = AXIS-VVP Full for signals in RX top/ TX top/ Du top signals table.
  • Updated note after RX top/ TX top/ Du top signals table.
  • Added Nios II Subsystem signals (Enable active video data protocols = AXIS-VVP Full) table.
  • Added additional description for Enable active video data protocols = AXIS-VVP Full for signals in Loopback top parameter table.
2021.04.04 22.1 19.2.1
  • Changed the title from F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide to F-Tile SDI II Intel FPGA IP Design Example User Guide.
  • Added files to Directory Structure for the Design Examples Figure and Other Generated Files in RTL Folder Table.
  • Removed Supported Verilog only from the following sections:
    • Simulating the Design
    • Hardware and Software Requirements
  • Added steps in Compiling and Testing the Design in Hardware.
  • Added Dynamic TX clock Switching parameters in Parameters available in Design Example tab Table.
  • Added Parallel loopback without external VCXO in Design Example Detailed Description.
  • Edited Quartus® Prime software version in Hardware and Software Requirements
  • Added DR Arbiter and DR IP to the following Figures:
    • Components required for TX and RX only design on Intel Agilex Device
    • Parallel loopback with simplex mode
    • Parallel loopback with duplex mode
    • Serial loopback with simplex mode
    • Serial loopback with duplex mode
  • Added new components to the following Tables:
    • Device Under Test (DUT) Components.
    • Loopback Top Components
    • Clocking Scheme Component
    • Top Level Signals
    • RX top/ TX top/ Du top parameters
    • RX top/ TX top/ Du top signals
    • Loopback top signals
  • Added triple-rate and multi-rate design in Test Description.
2022.01.28 21.4 19.2.0 Initial release.
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