F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer)
3.4. Design Parameters x
3.4.1. HDMI RX Direction 3.4.2. HDMI TX Direction
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System
3.9. Hardware Setup x
3.9.1. Supporting Additional Video Resolutions
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

2.5.3. Top-Level Common Blocks

The top-level common blocks include the transceiver arbiter, the RX-TX link components, and the CPU subsystem.
Table 14.  Top-Level Common Blocks
Module Description
RX-TX Link
  • The video data output and synchronization signals from HDMI RX core loop through a DCFIFO across the RX and TX video clock domains.
  • The auxiliary data port of the HDMI TX core controls the auxiliary data that flow through the DCFIFO through backpressure. The backpressure ensures there is no incomplete auxiliary packet on the auxiliary data port.
  • This block also performs external filtering:
    • Filters the audio data and audio clock regeneration packet from the auxiliary data stream before transmitting to the HDMI TX core auxiliary data port.
    • Filters the High Dynamic Range (HDR) InfoFrame from the HDMI RX auxiliary data and inserts an example HDR InfoFrame to the auxiliary data of the HDMI TX through the Avalon® streaming multiplexer.
CPU Subsystem

The CPU subsystem functions as SCDC and DDC controllers, and source reconfiguration controller.

  • The source SCDC controller contains the I2C master controller. The I2C master controller transfers the SCDC data structure from the FPGA source to the external sink for HDMI 2.0 operation. For example, if the outgoing data stream is 6,000 Mbps, the Nios® II processor commands the I2C master controller to update the TMDS_BIT_CLOCK_RATIO and SCRAMBLER_ENABLE bits of the sink TMDS configuration register to 1.
  • The same I2C master also transfers the DDC data structure (E-EDID) between the HDMI source and external sink.
  • The Nios® II CPU acts as the reconfiguration controller for the HDMI source. The CPU relies on the periodic rate detection from the RX Reconfiguration Management module to determine if the TX requires reconfiguration. The Avalon® memory-mapped slave translator provides the interface between the Nios® II processor Avalon® memory-mapped master interface and the Avalon® memory-mapped slave interfaces of the externally instantiated HDMI source’s IOPLL and TX PMA Direct PHY.
  • Perform link training through I2C master interface with external sink
IOPLL (vid_clk)
  • The IOPLL performs the following:
    • Generates the video clock. The reference clock to this IOPLL is 100 MHz clock.
    • Provides fix clock frequency which is 225 MHz.
F-tile Reference and System PLL Clock

This IP connects the System PLL output clock as well as the Tx PLL and Rx CDR reference clock to the F-tile PMA/FEC Direct PHY IP.

System PLL clock output shall always set to run at a higher clock frequency than the native PMA recovered clock.

For this design, the clock frequency is 900 MHz.

In F-tile HDMI Intel FPGA IP Design Example, F-tile Reference and System PLL Clock IP is configured to enable out_coreclk_1 which driven by Refclk #1 for FGT PMA.

The F-tile Reference and System PLL Clock IP configuration for the reference clock routed to the core feature in this design example is limited only for the HDMI application. For more information about the supported mode and configuration of the IP, refer to the Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP section of the F-tile Architecture and PMA and FEC Direct PHY IP User Guide.

Transceiver Reconfig Arbiter
  • This generic functional block prevents transceivers from simultaneous reconfiguration when either RX or TX transceivers within the same physical channel require reconfiguration. The simultaneous reconfiguration impacts applications where RX and TX transceivers within the same channel are assigned to independent IP implementations.
  • This transceiver arbiter is an extension to the resolution recommended for merging simplex TX and simplex RX into the same physical channel. This transceiver arbiter also assists in merging and arbitrating the Avalon® memory- mapped RX and TX reconfiguration requests targeting simplex RX and TX transceivers within a channel as the dynamic reconfiguration IP can only be accessed sequentially.
  • The interface connection between the transceiver arbiter and dynamic reconfiguration IP in this design example demonstrates a generic mode that applies for any IP combination using the transceiver arbiter. The transceiver arbiter is not required when only either RX or TX transceiver is used in a design. The transceiver arbiter identifies the requester of a reconfiguration through its Avalon memory-mapped reconfiguration interfaces and ensures that the corresponding reconfig_en[NUM_DR_CH-1:0] is gated accordingly. NUM_DR_CH is referring to number of reconfiguration requester in the design.
Dynamic Reconfig IP
  • Dynamic Reconfiguration (DR) IP is facilitated by NIOS. This includes inter-protocol switching or intra protocol link characteristic change such as link width or data rate switching.
  • For these use cases, DR can be triggered by either user application or Quartus NIOS utility. NIOS shall then perform the low level configuration register programming for various functional blocks.

HDMI example design using Dynamic Reconfiguration (DR) IP to reconfigure dynamically is a subset of the transceiver channels to operate in different modes (e.g. data rates) without impacting the adjacent active channels.

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