F-Tile JESD204C Intel® FPGA IP User Guide

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ID 691272
Date 2/10/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. F-Tile JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. System PLL
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the F-Tile JESD204C Intel® FPGA IP x
5.1. Reset Initialization 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Multi-Device Synchronization 5.7. Deterministic Latency 5.8. Transceiver Toolkit
5.1. Reset Initialization x
5.1.1. F-Tile JESD204C TX Reset Sequence 5.1.2. F-Tile JESD204C RX Reset Sequence
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
5.6. Multi-Device Synchronization x
5.6.1. Multi-Device DAC Application for Subclass 1 5.6.2. Multi-Device ADC Application for Subclass 1
5.7. Deterministic Latency x
5.7.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

3.1. Clocks

The F-Tile JESD204C IP runs on link clock (link layer) and frame clock (transport layer). The transceiver runs in the link clock domain and the serial clock domain.

Table 11.   F-Tile JESD204C IP Clocks
Clock Signal Formula Description

TX/RX device clock

j204c_pll_refclk

PLL selection The device clock is the PLL reference clock to the transceiver PLL.

TX/RX link clock

j204c_txlink_clk

j204c_rxlink_clk

Line rate/66 The timing reference for the F-Tile JESD204C IP. The link clock is line rate divided by 66 because the link clock operates in a 66-bit data bus domain architecture after 64B/66B encoding.

TX/RX frame clock

j204c_txframe_clk

j204c_rxframe_clk

(Link clock frequency*FCLK_MULP) MHz The frame clock as per the JESD204C specification. The frame clock is always 1x or 2x of the link clock.

TX/RX Avalon® memory-mapped clock

j204c_tx_avs_clk

j204c_rx_avs_clk

— The configuration clock for the F-Tile JESD204C IP control and status registers through the Avalon® memory-mapped interface. This clock is asynchronous to all the other clocks. The frequency range of this clock is 75 to 125 MHz.

TX PHY clock

j204c_phy_clk

Line rate/64

The PHY clock internally generated from the transceiver parallel clock for the TX path.
Transceiver reconfiguration clock

reconfig_xcvr_clk

— The transceiver reconfiguration clock. The frequency range of this clock is 100 MHz.
System PLL clock

sysclk

System PLL clock frequency >= Native clock frequency The F-Tile system PLL clock frequency is user-defined. The system PLL clock frequency is greater or equal to the native clock frequency.

Section Content
Device Clock
Frame Clock and Link Clock
System PLL

Level Two Title