4G Turbo-V Intel® FPGA IP User Guide

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ID 683882
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Getting Started with 4G Turbo-V IP 3. Designing with the 4G Turbo-V Intel® FPGA IP 4. 4G Turbo-V Intel® FPGA IP Functional Description 5. 4G Turbo-V Intel FPGA IP User Guide Document Archive 6. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. 4G Turbo-V IP Release Information 1.4. 4G Turbo-V Performance and Resource Utilization
2. Getting Started with 4G Turbo-V IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 4G Turbo-V IP Timeout Behavior
3. Designing with the 4G Turbo-V Intel® FPGA IP x
3.1. Generating a 4G Turbo-V IP 3.2. Simulating the IP with the RTL Simulator 3.3. Simulating a 4G Turbo-V IP with MATLAB 3.4. Simulating a 4G Turbo-V IP with C-Models
4. 4G Turbo-V Intel® FPGA IP Functional Description x
4.1. 4G Turbo-V Downlink Accelerator 4.2. 4G Turbo-V Uplink Accelerator 4.3. 4G Turbo-V Signals and Interfaces
4.1. 4G Turbo-V Downlink Accelerator x
4.1.1. Turbo Encoder 4.1.2. Rate Matcher 4.1.3. Input and Output Data Formats 4.1.4. Latency Calculations 4.1.5. Throughput Calculations
4.2. 4G Turbo-V Uplink Accelerator x
4.2.1. Turbo Decoder 4.2.2. Input and Output Data Formats 4.2.3. Latency Calculations 4.2.4. Throughput Calculations
4.3. 4G Turbo-V Signals and Interfaces x
4.3.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Getting Started with 4G Turbo-V IP
3. Designing with the 4G Turbo-V Intel® FPGA IP
4. 4G Turbo-V Intel® FPGA IP Functional Description
5. 4G Turbo-V Intel FPGA IP User Guide Document Archive
6. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

3.2. Simulating the IP with the RTL Simulator

Before simulating, generate a design example from the IP parameter editor. No hardware example gets generated when you click Generate Example Design. If you upgrade the IP to a newer version, regenerate the example design.
  1. To run the simulation with Synopsys VCS® simulator, run vcsmx_setup.sh from <example_design_directory>\simulation_scripts\synopsys\vcsmx\ directory by typing the following commands: 
    >> source vcsmx_setup.sh
>> simv
  2. To run the simulation with Cadence NCSim® simulator, run ncsim_setup.sh from <example_design_directory>\simulation_scripts\cadence\ directory by typing the following command: 
    sh ./ncsim_setup.sh USER_DEFINED_ELAB_OPTIONS='"-timescale 1ps/1ps"' USER_DEFINED_SIM_OPTIONS='"-input \"@run; exit\""'
  3. To run the simulation with Xcelium® simulator, run xcelium_setup.sh from <example_design_directory>\simulation_scripts\xcelium\ directory by typing the following command: 
    sh ./xcelium_setup.sh USER_DEFINED_ELAB_OPTIONS='"-timescale 1ps/1ps"' USER_DEFINED_SIM_OPTIONS='"-input \"@run; exit\""'
  4. To run the simulation with the ModelSim or Questa® simulator, run msim_setup.tcl from <example_design_directory>\simulation_scripts\mentor\ directory by typing the following commands: 
    vsim -c do msim_setup.tcl
ld
run -all
  5. To run the simulation with Aldec® simulator. run rivierapro_setup.tcl from <example_design_directory>\simulation_scripts\aldec\ directory by typing the following commands: 
    vsim -c do rivierapro_setup.tcl
ld
run -all
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