F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing

This section details the steps you should follow to configure the F-Tile PMA/FEC Direct PHY Intel® FPGA IP in order to bring-up the FHT or FGT PMA for hardware testing using System Console in the Intel® Quartus® Prime software. You can configure the PMA analog settings to enable functions such as serial loopback, PRBS generators and checkers, to modify TX equalizer settings, and BER measurements.

You can instantiate two Avalon® memory-mapped interfaces for duplex, simplex TX, and simplex RX designs:
  • Connect Avalon® memory-mapped interface 1 to the Datapath Avalon® memory-mapped interface.
  • Connect Avalon® memory-mapped interface 2 to the PMA Avalon® memory-mapped interface.
You can instantiate four Avalon® memory-mapped Interfaces for dual simplex designs, where you place the simplex TX and simplex RX IPs at the same transceiver location:
  • Connect Avalon® memory-mapped interface 1 to the Datapath Avalon® memory-mapped interface of the simplex TX IP.
  • Connect Avalon® memory-mapped interface 2 to the PMA Avalon® memory-mapped interface of the simplex TX IP.
  • Connect Avalon® memory-mapped interface 3 to the Datapath Avalon® memory-mapped interface of the simplex RX IP.
  • Connect Avalon® memory-mapped interface 4 to the PMA Avalon® memory-mapped interface of the simplex RX IP.
Note:
  • The Avalon® memory-mapped interface 1 and 3 can access the Datapath Avalon® memory-mapped interfaces of both simplex TX and RX IPs.
  • The Avalon® memory-mapped interface 2 and 4 can access the PMA Avalon® memory-mapped interfaces of both simplex TX and RX IPs.

You can choose either of the following methods to access the PMA registers via JTAG using System Console: