Visible to Intel only — GUID: hka1553244979725
Ixiasoft
Visible to Intel only — GUID: hka1553244979725
Ixiasoft
4.1.5.1. Running the Design Example in Hardware
If you select Intel Agilex® 7 F-Series Transceiver-SoC Development Kit option as the Target Development Kit in the E-Tile Dynamic Reconfiguration Design Example parameter editor in Quartus® Prime Pro Edition software, refer to Power Management Setting for Agilex 7 Transceiver Signal Integrity Development Kit on how to configure the power management setting that can be included in the Quartus Setting File (.qsf) for the Intel Agilex® 7 F-Series Transceiver-SoC Development Kit.
Follow the steps below to run the design example in hardware:
- In the Quartus® Prime Pro Edition software, compile the design example with the power management setting included to obtain a working SRAM Object File (.sof) file.
- Download the .sof file to the Intel Agilex® 7 F-Series Transceiver-SoC Development Kit .
- Launch the Clock Control application and set new frequencies for the design example. Below is the frequency setting in the Clock Control application. Select Si5341A(U3) to program:
- U34, OUT0 = 156.25 MHz
- U36, OUT1 = 100 MHz
- U37, OUT2 = 153.6 MHz for the CPRI designs that target 24.3 Gbps CPRI with RS-FEC line rates.
This step is only applicable for CPRI protocol and Ethernet to CPRI protocol related dynamic reconfiguration design examples.
- In the <design_example_dir>/software/dynamic_reconfiguration_hardware folder, execute the following commands:
- Execute the command niosv-bsp -c --quartus-project=../../hardware_test_design/alt_ehipc3.qpf --qsys=../../hardware_test_design/nios_system.qsys --type=hal etile_dr_cpu_bsp/settings.bsp to generate the BSP files.
- At the same path, execute the command niosv-app --bsp-dir=etile_dr_cpu_bsp --app-dir=etile_dr_cpu_app --srcs=. --elfname=etile_dr_cpu.elf to generate the user application CMakeLists.txt.
- Run the Eclipse-based Ashling Riscfree IDE Tool launcher.
- Create a new workspace when the Workspace Launcher window prompt appears.
- Click Launch to open the workspace.
- In the Eclipse-based Ashling Riscfree IDE Tool window, select File > New > Project. A New Project window appears.
- Choose C/C++ > C/C++ Project > C++ Managed Build.
- For the Project name, specify your desired project name. This example uses dynamic_reconfiguration_hardware.
- For project type, select CMake driven > Empty Project. For Toolchains, select CMake driven.
- Click Finish. The CMake driven application is added to the Project Explorer.
- Uncheck Use default location. Navigate to <example_design_dir>/software/dynamic_reconfiguration_hardware/etile_dr_cpu_app to locate the CMakeLists.txt in the NIOS V application project.
- On the Project Explorer view, right-click the project and select Build Project. Ensure the etile_dr_cpu.elf file is generated in the <design_example_dir>/software/dynamic_reconfiguration_hardware/etile_dr_cpu_app/build/Debug directory.
- On the Project Explorer view, right-click the project and select Run as > Run Configurations....
- Select Ashling RISC-V Hardware Debugging > New Configuration.
- Under the Main tab, make sure that the Project matches the project name (dynamic_reconfiguration_hardware).
- In C/C++ Application, click Browse and navigate to the etile_dr_cpu.elf file generated in the <design_example_dir>/ software/dynamic_reconfiguration_hardware/etile_dr_cpu_app/build/Debug directory.
- Click Apply to apply the changes.
- Under the Debugger tab, set the Debug Probe Configuration according to the board settings.
- Select Auto-detect Scan Chain in Target Configuration to automatically detect JTAG scan chain information of the target device. Ensure the detected Device/TAP selection is correct and core selection is Nios® V .
- Check the Issue Tap reset option.
- Click Apply to apply the changes.
- Once the configuration is set, click Run. If the configuration is successful, the following debug console is displayed.
- To view the output of JTAG UART terminal in Eclipse-based Ashling RiscFree IDE Tool, select Run > External Tools > External Tools Configuration... from the tool drop-down menu.
- Select Program and click New Launch Configuration. Rename the configuration as Nios® V JTAG UART Output.
- Under the Main tab, select Browse > File System... and navigate to the path for JTAG UART terminal.
- For Linux: <Intel Quartus Prime installation directory>/quartus/linux64/juart-terminal
- For Windows: <Intel Quartus Prime installation directory>/quartus/bin64/juart-terminal.exe
- In Arguments, enter the -c 1 -d 0 -i 0
- Under the Main tab, select Browse > File System... and navigate to the path for JTAG UART terminal.
- Click Apply to save the changes, then click Run to generate the program.
Note: The GUI dialog box varies based on the selected dynamic reconfiguration hardware test variant.
- In the Interactive GUI dialog box, select the dynamic reconfiguration hardware test.
The following is a hardware test example for the 25G Ethernet with PTP and RS-FEC variant.
CPU is alive! Dynamic Reconfiguration Hardware Test By default, the starting mode is 25G_PTP_FEC. Please choose one of Dynamic reconfiguration: 0) 25G_PTP_FEC -> 25G_PTP_noFEC -> 10G_PTP -> 25G_PTP_noFEC -> 25G_PTP_FEC -> 10G_PTP -> 25G_PTP_FEC 1) 25G_PTP_FEC -> 25G_PTP_noFEC 2) 25G_PTP_noFEC -> 25G_PTP_FEC 3) 25G_PTP_FEC -> 10G_PTP 4) 10G_PTP -> 25G_PTP_FEC 5) 25G_PTP_noFEC -> 10G_PTP 6) 10G_PTP -> 25G_PTP_noFEC 9) Terminate test If you terminate test halfway, you must reload the .sof file before retrigger the hardware test. Enter a Valid Selection (0,1,3,9):
The following is a hardware test example for CPRI variants.
CPU is alive! Dynamic Reconfiguration Hardware Test By default, the starting mode is CPRI24G_FEC. Please choose the Targeted mode available: 1) CPRI24G 2) CPRI12GFEC 3) CPRI12G 4) CPRI10GFEC 5) CPRI10G 6) CPRI9.8G 7) CPRI6.0G 8) CPRI4.9G 9) CPRI3.0G a) CPRI2.4G 9) Terminate test -> If you terminate test halfway, you must reload the .sof file before retrigger the hardware test. Enter a Valid Selection: