E-Tile Hard IP Agilex™ 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 4/30/2024
Public
Document Table of Contents

4.1.5.2. Power Management Setting for Agilex™ 7 Transceiver Signal Integrity Development Kit

If you select Intel Agilex® 7 F-Series Transceiver-SoC Development Kit option as the Target Development Kit in the E-Tile Dynamic Reconfiguration Design Example parameter editor in Quartus® Prime Pro Edition software, the target device used for the design example is set to default AGFB014R24A2E2VR0 with the pin assignments provided in the .qsf file.

The Intel Agilex® 7 F-Series Transceiver-SoC Development Kit (AGFB014R24A2E2VR0) is a voltage identification (VID) device. The .qsf file includes the power management setting. The following is an example of the specific power management setting that can be included in the .qsf file for the Intel Agilex® 7 F-Series Transceiver-SoC Development Kit:

set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
set_global_assignment -name USE_PWRMGT_SDA SDM_IO12
set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ"
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 42
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 43
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 44
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00
set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "AUTO DISCOVERY"
set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS”

However, if you select the Other Development Kits option as the Target Development Kit, the target device used for the design example follows the target device chosen in the project. You must set the pin assignment based on the base variant used.

Note: The E-Tile Dynamic Reconfiguration Design Example is a Nios® V-based design. You can use the Eclipse-based Ashling RiscFree IDE Tool to perform the hardware test.