E-Tile Dynamic Reconfiguration Design Example Release Notes

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ID 683851
Date 4/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. E-Tile Dynamic Reconfiguration Design Example Release Notes
1. E-Tile Dynamic Reconfiguration Design Example Release Notes x
1.1. E-Tile Dynamic Reconfiguration Design Example v21.0.0 1.2. E-Tile Dynamic Reconfiguration Design Example v20.2.0 1.3. E-Tile Dynamic Reconfiguration Design Example v20.1.0 1.4. E-Tile Dynamic Reconfiguration Design Example v19.4.0 1.5. E-Tile Dynamic Reconfiguration Design Example v19.3.0 1.6. E-Tile Dynamic Reconfiguration Design Example v19.2.0 1.7. E-Tile Dynamic Reconfiguration Design Example v19.1 1.8. E-Tile Dynamic Reconfiguration Design Example User Guide Archives
1. E-Tile Dynamic Reconfiguration Design Example Release Notes

1.1. E-Tile Dynamic Reconfiguration Design Example v21.0.0

Table 1.  v21.0.0 2024.04.01
Quartus® Prime Version Description Impact
24.1 Changed Nios® implementation from Nios® II to Nios® V in the E-Tile Dynamic Reconfiguration Design Example. —

Some Intel® FPGA IP products that previously included a Nios® II processor now use a Nios® V processor.

If you do not have a valid Nios® V license, you might receive an error message when you generate programming files for a design that includes these Intel® FPGA IP products.

For details and a workaround, refer to Why do I get an error in generating programming files and it shows as invalid license for Nios® V Processor for Intel® FPGA in the Quartus® Prime Pro Edition software version 24.1? in the Intel® FPGA Knowledge Base.

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