External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683842
Date 3/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Arria® 10 FPGA IP 2. Design Example Description for External Memory Interfaces Intel® Arria® 10 FPGA IP 3. Document Revision History for External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Arria® 10 FPGA IP x
1.1. Creating an EMIF Project 1.2. Generating and Configuring the EMIF IP 1.3. Generating the Synthesizable EMIF Design Example 1.4. Generating the EMIF Design Example for Simulation 1.5. Simulation Versus Hardware Implementation 1.6. Simulating External Memory Interface IP With ModelSim 1.7. Pin Placement for Intel® Arria® 10 EMIF IP 1.8. Compiling and Programming the Intel® Arria® 10 EMIF Design Example 1.9. Debugging the Intel® Arria® 10 EMIF Design Example
1.2. Generating and Configuring the EMIF IP x
1.2.1. Intel® Arria® 10 EMIF Parameter Editor Guidelines
2. Design Example Description for External Memory Interfaces Intel® Arria® 10 FPGA IP x
2.1. Synthesis Example Design 2.2. Simulation Example Design 2.3. Example Designs Interface Tab
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Arria® 10 FPGA IP
2. Design Example Description for External Memory Interfaces Intel® Arria® 10 FPGA IP
3. Document Revision History for External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide

1.7. Pin Placement for Intel® Arria® 10 EMIF IP

This topic provides guidelines for pin placement.

Overview

Intel® Arria® 10 FPGAs have the following structure:
  • Each device contains 2 I/O columns.
  • Each I/O column contains up to 8 I/O banks.
  • Each I/O bank contains 4 lanes.
  • Each lane contains 12 general-purpose I/O (GPIO) pins.

General Pin Guidelines

The following points provide general pin guidelines:

  • Ensure that the pins for a given external memory interface reside within a single I/O column.
  • Interfaces that span multiple banks must meet the following requirements:
    • The banks must be adjacent to one another. For information on adjacent banks, refer to the Intel Arria 10 External Memory Interfaces IP User Guide.
    • The address and command bank must reside in a center bank to minimize latency. If the memory interface uses an even number of banks, the address and command bank may reside in either of the two center banks.
  • Unused pins can be used as general-purpose I/O pins.
  • All address and command and associated pins must reside within a single bank.
  • Address and command and data pins can share a bank under the following conditions:
    • Address and command and data pins cannot share an I/O lane.
    • Only an unused I/O lane in the address and command bank can be used for data pins.
Table 4.  General Pin Constraints
Signal Type Constraint
Data Strobe All signals belonging to a DQ group must reside in the same I/O lane.
Data Related DQ pins must reside in the same I/O lane. DM/DBI pins must be paired off with a DQ pin for proper operation. For protocols that do not support bidirectional data lines, read signals should be grouped separately from write signals.
Address and Command Address and Command pins must reside in predefined locations within an I/O bank.

Pin Assignments

If you applied a development kit preset during IP generation, all pin assignments for the development kit are automatically generated and can be verified in the .qsf file that is generated with the design example.

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