External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide

Download PDF
ID 683842
Date 3/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Arria® 10 FPGA IP 2. Design Example Description for External Memory Interfaces Intel® Arria® 10 FPGA IP 3. Document Revision History for External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Arria® 10 FPGA IP x
1.1. Creating an EMIF Project 1.2. Generating and Configuring the EMIF IP 1.3. Generating the Synthesizable EMIF Design Example 1.4. Generating the EMIF Design Example for Simulation 1.5. Simulation Versus Hardware Implementation 1.6. Simulating External Memory Interface IP With ModelSim 1.7. Pin Placement for Intel® Arria® 10 EMIF IP 1.8. Compiling and Programming the Intel® Arria® 10 EMIF Design Example 1.9. Debugging the Intel® Arria® 10 EMIF Design Example
1.2. Generating and Configuring the EMIF IP x
1.2.1. Intel® Arria® 10 EMIF Parameter Editor Guidelines
2. Design Example Description for External Memory Interfaces Intel® Arria® 10 FPGA IP x
2.1. Synthesis Example Design 2.2. Simulation Example Design 2.3. Example Designs Interface Tab
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Arria® 10 FPGA IP
2. Design Example Description for External Memory Interfaces Intel® Arria® 10 FPGA IP
3. Document Revision History for External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide

1.3. Generating the Synthesizable EMIF Design Example

For the Intel® Arria® 10 development kits, there are presets that automatically parameterize the EMIF IP and generate pinouts for the specific board.
  1. Verify that the Presets window is visible. If the Presets window is not visible, display it by selecting View > Presets.
  2. In the Presets window, select the appropriate development kit preset and click Apply.

  3. Configure the EMIF IP and click Generate Example Design in the upper-right corner of the window.

  4. Specify a directory for the EMIF design example and click OK. Successful generation of the EMIF design example creates the following fileset under a qii directory.
Figure 3. Generated Synthesizable Design Example File Structure
Note:

If you don't select the Simulation or Synthesis checkbox, the destination directory will contain Platform Designer design files, which are not compilable by the Intel® Quartus® Prime software directly, but can be viewed or edited under the Platform Designer. In this situation you can run the following commands to generate synthesis and simulation file sets.

  • To create a compilable project, you must run the quartus_sh -t make_qii_design.tcl script in the destination directory.
  • To create a simulation project, you must run the quartus_sh -t make_sim_design.tcl script in the destination directory.

The Select board pulldown in this section applies the appropriate development kit pin assignments to the example design.

  • This setting is available only when you turn on the Synthesis checkbox in the Example Design Files section.
  • This setting must match the applied development kit present, or else an error message appears.

If the value None appears in the Select board pulldown, it indicates that the current parameter selections do not match any development kit configurations. You may apply a development kit-specific IP and related parameter settings by selecting one of the presets from the preset library. When you apply a preset, the current IP and other parameter settings are set to match the selected preset. If you want to save your current settings, you should do so before you select a preset. If you do select a preset without saving your prior settings, you can always save the new preset settings under a different name

If you want to generate the example design for use on your own board, set Select board to None, generate the example design, and then add pin location constraints.

Related Information
Level Two Title