External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide

Download PDF
ID 683842
Date 3/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Arria® 10 FPGA IP 2. Design Example Description for External Memory Interfaces Intel® Arria® 10 FPGA IP 3. Document Revision History for External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Arria® 10 FPGA IP x
1.1. Creating an EMIF Project 1.2. Generating and Configuring the EMIF IP 1.3. Generating the Synthesizable EMIF Design Example 1.4. Generating the EMIF Design Example for Simulation 1.5. Simulation Versus Hardware Implementation 1.6. Simulating External Memory Interface IP With ModelSim 1.7. Pin Placement for Intel® Arria® 10 EMIF IP 1.8. Compiling and Programming the Intel® Arria® 10 EMIF Design Example 1.9. Debugging the Intel® Arria® 10 EMIF Design Example
1.2. Generating and Configuring the EMIF IP x
1.2.1. Intel® Arria® 10 EMIF Parameter Editor Guidelines
2. Design Example Description for External Memory Interfaces Intel® Arria® 10 FPGA IP x
2.1. Synthesis Example Design 2.2. Simulation Example Design 2.3. Example Designs Interface Tab
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Arria® 10 FPGA IP
2. Design Example Description for External Memory Interfaces Intel® Arria® 10 FPGA IP
3. Document Revision History for External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide

2.3. Example Designs Interface Tab

The parameter editor includes an Example Designs tab which allows you to parameterize and generate your example designs. l

Figure 11. Example Designs Tab in the External Memory Interfaces Parameter Editor

Available Example Designs Section

The Select design pulldown allows you to select the desired example design. At present, EMIF Example Design is the only available choice, and is selected by default.

Level Two Title