2021.10.01 |
21.2 |
1.3.1 |
- Added support for the Intel® Agilex™ F-tile devices.
- Added support for multi-channel designs.
- Updated Table: eCPRI Intel FPGA IP Hardware Design Example Register Map.
- Removed support for NCSim.
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2021.02.26 |
20.4 |
1.3.0 |
- Added support for the Intel® Agilex™ E-tile devices.
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2021.01.08 |
20.3 |
1.2.0 |
- Changed the document title from eCPRI Intel Stratix 10 FPGA IP Design Example User Guide to eCPRI Intel FPGA IP Design Example User Guide.
- Added support for Intel® Arria® 10 designs.
- The eCPRI IP design example is now available with interworking function (IWF) feature support.
- Added a note to clarify that eCPRI design example with IWF feature is only available for 9.8 Gbps CPRI line bit rate.
- Added conditions in section Generating the Design when generating the design example with Interworking Function (IWF) Support parameter enabled.
- Added sample simulation test run output with IWF feature enabled in section Simulating the Design Example Testbench.
- Added new section Enabling Dynamic Reconfiguration to the Ethernet IP.
- Updated hardware test sample output in section Testing the eCPRI Intel FPGA IP Design Example.
- Updated the Figure: eCPRI Intel FPGA IP Hardware Design Examples High Level Block Diagram to include IWF Type 0, CPRI MAC, and CPRI PHY blocks.
- Updated Table: Design Example Interface Signals to include Intel® Arria® 10 device and IWF related signals.
- Updated Table: eCPRI Intel FPGA IP Hardware Design Example Register Map.
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2020.06.15 |
20.1 |
1.1.0 |
- Added support for 10G data rate.
- flow.c file is now available with design example generation to select loopback mode.
- Modified the sample output for simulation test run in section Simulating the Design Example Testbench.
- Added frequency value for running 10G data rate design in section Compiling and Configuring the Design Example in Hardware.
- Made following changes in section Testing the eCPRI Intel FPGA IP Design Example:
- Added commands to switch data rate between 10G and 25G
- Added sample output for data rate switching
- Added TEST_MODE variable information to select loopback in E-tile device variations.
- Modified eCPRI Intel FPGA IP Hardware Design Examples High Level Block Diagram to include new blocks.
- Updated Table: Design Example Interface Signals to include new signal.
- Updated Design Example Register Map section.
- Added new appendix section:Generating and Downloading the Executable and Linking Format (.elf) Programming File .
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2020.04.13 |
19.4 |
1.0.0 |
Initial release. |