25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683833
Date 12/14/2020
Public
Document Table of Contents
Document Table of Contents x
1. 25G Ethernet Intel FPGA IP Quick Start Guide 2. Design Example Description 3. 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide
1. 25G Ethernet Intel FPGA IP Quick Start Guide x
1.1. Design Example Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the 25G Ethernet Intel FPGA IP Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the 25G Ethernet Intel FPGA IP Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. 25G Ethernet Intel FPGA IP Design Example Registers
1. 25G Ethernet Intel FPGA IP Quick Start Guide
2. Design Example Description
3. 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide

2.2. Design Example Interface Signals

The 25G Ethernet Intel FPGA IP testbench is self-contained and does not require you to drive any input signals.

Table 4.   25G Ethernet Intel FPGA IP Hardware Design Example Interface Signals
Signal Direction Comments
clk50 Input Drive at 50 MHz. The intent is to drive this from a 50 Mhz oscillator on the board.
clk_ref Input Drive at 644.53125 MHz.
cpu_resetn Input Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core.
tx_serial Output Transceiver PHY output serial data.
rx_serial Input Transceiver PHY input serial data.
user_led[7:0] Output Status signals. The hardware design example connects these bits to drive LEDs on the target board. Individual bits reflect the following signal values and clock behavior:
  • [0]: Main reset signal to IP core
  • [1]: Divided version of clk_ref
  • [2]: Divided version of clk50
  • [3]: Divided version of 100 MHz status clock
  • [4]: tx_lanes_stable
  • [5]: rx_block_lock
  • [6]: rx_am_lock
  • [7]: rx_pcs_ready
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