Networking Interface for Open Programmable Acceleration Engine: Intel FPGA Programmable Acceleration Card D5005

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ID 683830
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Overview 3. Partial Reconfiguration HSSI Interface 4. Native PHY IP Core Parameters 5. OPAE Support 6. Document Revision History for Networking Interface for OPAE
1. About this Document x
1.1. Conventions 1.2. Acceleration Glossary
2. Overview x
2.1. Logical View 2.2. Physical View 2.3. Clock Architecture
3. Partial Reconfiguration HSSI Interface x
3.1. Clock Signals 3.2. Data Interface and Signals 3.3. Control and Status Signals 3.4. Connecting the PCS to the HSSI Interface
5. OPAE Support x
5.1. Supported Settings 5.2. Unsupported Settings 5.3. Tuning Information
1. About this Document
2. Overview
3. Partial Reconfiguration HSSI Interface
4. Native PHY IP Core Parameters
5. OPAE Support
6. Document Revision History for Networking Interface for OPAE

1. About this Document

Updated for:
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 2.0.1
This document describes how to integrate the network port feature into an Accelerator Functional Unit (AFU) and provision it from the host using the Open Programmable Acceleration Engine (OPAE) driver and tools. This document provides information about:
  • Partial Reconfiguration High Speed Serial Interface (HSSI)
  • Intel® Stratix® 10 Native PHY IP core parameters
  • Tuning analog settings
Level Two Title