AN 500: NAND Flash Memory Interface with Altera MAX Series

Download PDF
ID 683829
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. NAND Flash Memory Interface with Altera MAX Series
1. NAND Flash Memory Interface with Altera MAX Series x
1.1. NAND Flash Interface Using Altera Devices 1.2. Implementation 1.3. Acknowledgments 1.4. Document Revision History
1.1. NAND Flash Interface Using Altera Devices x
1.1.1. Signals 1.1.2. Operations 1.1.3. AMD and Samsung NAND Flash Devices Commands
1.2. Implementation x
1.2.1. Source Code
1. NAND Flash Memory Interface with Altera MAX Series

1.1.1. Signals

Table 1.  Interfacing SignalsThis table lists the interfacing signals.
Signal Size Description
READ/WRITE# 1-bit Input from the microprocessor to distinguish between a write and a read operation.
  • READ/WRITE# 0: Write operation.
  • READ/WRITE# 1: Read operation
RESET 1-bit Input from the microprocessor to reset the NAND Flash device.
CONTROL[2:0] 3-bit 3-bit control bus. The microprocessor sends 3 bits of information to the NAND Flash interface (supported Altera devices) where it is suitably decoded. The appropriate interfacing signals are enabled or disabled depending on the condition of the EN/DB# input.
EN/DB# 1-bit Control bit used in conjunction with the control bits to perform the required operation.
  • EN/DB# 1: Enables the interfacing signal selected by the control bits
  • EN/DB# 0: Disables the interfacing signal selected by the control bits.
I/O[7:0] 8-bit Bidirectional 8-bit multiplexed bus used to send data/command/address to their respective registers in the NAND Flash device. The data read from the NAND Flash device is also available on these lines.
RY/BY# 1-bit Output from the NAND Flash device, indicating the status of the device.
  • RY/BY# 0 : Device is still busy performing an operation.
  • RY/BY# 1 : Device is ready to accept the next command.
CLE 1-bit Active high Command Latch Enable. Use to select the Command Register or the Data Register of the device. When high, the command on the I/O lines is latched into the command register on the rising edge of WE#.
Note: Data Register is selected by making the CLE and ALE signals low. The data on the I/O lines is latched into the Data Register on the rising edge of WE#.
ALE 1-bit Active high Address Latch Enable. Use to select the Address Register or the Data Register of the device. When high, the address on the I/O lines is latched into the address register on the rising edge of WE#. A low signal will cause the device to reset. This signal must remain high for the entire address sequence.
Note: Data Register is selected by making the CLE and ALE signals low. The data on the I/O lines is latched into the Data Register on the rising edge of WE#.
CE# 1-bit Active low Chip Enable. Use to choose between the active mode and the standby mode of the device.
  • CE# 0 : Active mode selected.
  • CE# 1 : Standby mode is selected if no operation is currently in progress.
The CE signal is ignored if a program or erase operation is in progress.
WE# 1-bit Active low Write Enable. Use to write command/address/data into their respective registers in the device. The information on the I/O lines is latched into the respective registers on the rising edge of WE#.
WP# 1-bit Active low Write Protect.
  • WP# 0 : Device is write protected.
  • WP# 1 : Device is not write protected.
RE# 1-bit Active low Read Enable. Use to read data/status to/from the device. The information is available on the I/O lines on the rising edge of RE#.
SE# 1-bit Active low Spare area Enable. Required only when an AMD device is used. Not required for a Samsung device.
  • SE# 0 : 16 bytes of Spare area on each page is enabled.
  • SE# 1 : Spare area is disabled.
Level Two Title