AN 818: Static Update Partial Reconfiguration Tutorial: for Intel® Stratix® 10 GX FPGA Development Board

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ID 683826
Date 5/12/2021
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Document Table of Contents
Document Table of Contents x
1. Static Update Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board
1. Static Update Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board x
1.1. Tutorial Requirements 1.2. Reference Design Overview 1.3. Static Update Region Overview 1.4. Download Reference Design Files 1.5. Reference Design Walkthrough 1.6. Static Update Partial Reconfiguration Tutorial Revision History
1.5. Reference Design Walkthrough x
1.5.1. Step 1: Getting Started 1.5.2. Step 2: Create Design Partitions 1.5.3. Step 3: Allocate Placement and Routing Regions 1.5.4. Step 4: Define Personas 1.5.5. Step 5: Create Revisions 1.5.6. Step 6: Compile the Base Revision 1.5.7. Step 7: Set Up PR Implementation Revisions 1.5.8. Step 8: Change the SUPR Logic 1.5.9. Step 9: Program the Board 1.5.10. Modifying the SUPR Partition
1.5.5. Step 5: Create Revisions x
1.5.5.1. Setting the Base Revision 1.5.5.2. Creating Implementation Revisions
1.5.9. Step 9: Program the Board x
1.5.9.1. Troubleshooting PR Programming Errors
1. Static Update Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board

1.5.9. Step 9: Program the Board

Follow these steps to connect and program the Intel® Stratix® 10 GX FPGA development board:
  1. Connect the power supply to the Intel® Stratix® 10 GX FPGA development board.
  2. Connect a USB cable between your PC USB port and the USB programming hardware on the development board.
  3. Open the Intel® Quartus® Prime software, and then click Tools > Programmer.
  4. In the Programmer, click Hardware Setup, and then select USB-Blaster.
  5. Click Auto Detect, and then select the 1SG280LU5S1 device.
  6. Click OK. The Intel® Quartus® Prime software detects and updates the Programmer with the three FPGA devices on the board.
  7. Select the 1SG280LU5S1 device, click Change File, and load the blinking_led_default.sof file.
  8. Enable Program/Configure for the blinking_led_default.sof file.
  9. Click Start and wait for the progress bar to reach 100%.
  10. Observe the LEDs on the board blinking.
  11. To program only the PR region, right-click the blinking_led_default.sof file in the Programmer and click Add PR Programming File.
  12. Select the blinking_led_slow.pr_partition.rbf file.
  13. Disable Program/Configure for the blinking_led_default.sof file.
  14. Enable Program/Configure for the blinking_led_slow.pr_partition.rbf file, and then click Start. On the board, observe LED[0] and LED[1] continuing to blink. When the progress bar reaches 100%, LED[2] and LED[3] blink slower.
    Figure 11. Programming the Intel® Stratix® 10 GX FPGA Development Board
  15. To re-program the PR region, right-click the .rbf file in the Programmer, and then click Change PR Programing File.
  16. Select the .rbf files for the other two personas to observe the behavior on the board. Loading the blinking_led_default.pr_partition.rbf file causes the LEDs to blink at the original frequency, and loading the blinking_led_empty.pr_partition.rbf file causes the LEDs to stay ON.
  17. To change the SUPR logic, repeat step 7 above to select the impl_blinking_led_supr_new.sof. After changing this file, led [0:1] now blinks at a faster rate than before. The other PR .rbf files are also compatible with the new .sof.
Note:

The Assembler generates an .rbf file for the SUPR region. However, you should not use this file to reprogram the FPGA at runtime because the SUPR partition does not instantiate the freeze bridge, PR region controller, and other logic in the overall system. When you make changes to the SUPR partition logic, you must reprogram the full .sof file from the SUPR implementation revision compilation.


Section Content
Troubleshooting PR Programming Errors

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