AN 906: Intel® Stratix® 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines

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ID 683813
Date 2/06/2020
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Document Table of Contents x
1. AN 906: Intel® Stratix® 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines
1. AN 906: Intel® Stratix® 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines x
1.1. Device Area Constraints 1.2. Document Revision History for AN 906: Intel® Stratix® 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines
1.1. Device Area Constraints x
1.1.1. Chip Layout 1.1.2. Floorplan Restrictions 1.1.3. Logic Utilization
1.1.2. Floorplan Restrictions x
1.1.2.1. Possible Congestion Areas 1.1.2.2. HPS-to-Core and I/O-to-Core Traffic 1.1.2.3. HPS Chimney 1.1.2.4. EMIF Usage
1.1.2.1. Possible Congestion Areas x
1.1.2.1.1. HPS and I/O Bank 3D Top-right Area 1.1.2.1.2. SDM and I/O Bank 3A Bottom-right Area
1. AN 906: Intel® Stratix® 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines

1.1.2.4. EMIF Usage

Figure 6. EMIF Usage

There is a risk of closing timing in the EMIF usage on banks 3B and 3C if the HPS and secure device manager (SDM) usage on top and bottom provides congestion in areas crossing the EMIF logic interfaces. Proper usage placement of EMIFs helps lessen the congestion.

You will be unable to access the EMIF usage on banks 3A and 3D due to a high risk of not being able to meet timing. Logic and memory resources available aggravated by routability issues at the right-bottom corner between the SDM and EMIF bank 3A and at the top-right corner between the HPS and EMIF bank 3D make it hard to meet timing closure.

Table 1.  Bank 3A, Bank 3B, Bank 3C, and Bank 3D Usage in Intel® Stratix® 10 GX 400, SX 400, and TX 400 Devices
Bank Intel® Stratix® 10 TX 400 (1ST040) Intel® Stratix® 10 GX 400 (1SG040) and SX 400 (1SX040)
3A Use for any general-purpose I/O (GPIO) Use for GPIO only
3B Use for GPIO, EMIF, or LVDS Use for GPIO, EMIF, or LVDS
3C Use for GPIO, EMIF, or LVDS Use for 3.3V GPIOs only
3D Use for any GPIO Use for 1.8V GPIO only (it has 30 pins)

Real-design experiments will determine if a combination of HPS, SDM, and EMIFs on the right column is feasible.

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