Intel® FPGA Programmable Acceleration Card D5005 Board Management Controller User Guide

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ID 683811
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel FPGA Programmable Acceleration Card D5005 BMC Introduction 2. PLDM over MCTP SMBus 3. EEPROM Data Format 4. Revision History
1. Intel FPGA Programmable Acceleration Card D5005 BMC Introduction x
1.1. About this document 1.2. Overview 1.3. Root of Trust (RoT) 1.4. Power Sequence Management 1.5. Board Monitoring Through Sensors 1.6. Secure Remote System Update 1.7. FRUID EEPROM 1.8. MAC Address EEPROM
2. PLDM over MCTP SMBus x
2.1. SMBus Slave Address 2.2. SMBus Interface Speed 2.3. MCTP Packetization Support 2.4. Supported Command Sets 2.5. PLDM Topology and Hierarchy 2.6. Board Monitoring through I2C SMBus
1. Intel FPGA Programmable Acceleration Card D5005 BMC Introduction
2. PLDM over MCTP SMBus
3. EEPROM Data Format
4. Revision History

1.1. About this document

Reference the Intel FPGA Programmable Acceleration Card D5005 Board Management User Guide to learn more about the functions and features of the Intel® MAX® 10 BMC and to understand how to read telemetry data on the Intel FPGA Programmable Acceleration Card D5005 using I2C and SMBus. An introduction to Intel® MAX® 10 root of trust (RoT) and secure remote system update is included.

Note: Throughout this document, any mention of Intel® FPGA PAC or Intel® FPGA PAC D5005 shall specifically refer to the Intel FPGA Programmable Acceleration Card D5005.
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